Abstract: A two-dimensional scatter plot is created by plotting the gray levels of pixels from a test image against the gray levels of corresponding pixels from a reference image. A noise reduction filter is applied on the scatter plot to define a mask shape which can be extracted and filled-in to generate a mask. Defect pixels on the test image are identified by comparing corresponding pixel gray values against the mask. A typical application is detecting defects in a semiconductor wafer during device fabrication.

Abstract: The present invention relates to methods and procedures for determining resist temperature during energy beam lithography and adjusting process parameters, including reducing the beam current, to compensate for increased resist sensitivity due to heating. The present invention relates to methods of predicting resist heating in real-time as the writing proceeds thereby enabling beam compensation to be performed in real-time. A linear superposition approximation is described that provides a procedure for estimating the resist temperature at the point presently being written from previously written points. The present invention makes use of the thermal history of the pattern previously written as that history is recorded in the line of pixels immediately preceding the line whose temperature is to be determined prior to e-beam exposure, and a single number representing the thermal history of lines written before the immediately preceding line.

Abstract: A photocathode having a gate electrode so that modulation of the resulting electron beam is accomplished independently of the laser beam. The photocathode includes a transparent substrate, a photoemitter, and an electrically separate gate electrode surrounding an emission region of the photoemitter. The electron beam emission from the emission region is modulated by voltages supplied to the gate electrode. In addition, the gate electrode may have multiple segments that are capable of shaping the electron beam in response to voltages supplied individually to each of the multiple segments.

Abstract: A programmable logic device includes a global clock structure and a plurality of localized clock structures. Each localized clock structure distributes a respective localized clock signal to a corresponding portion of the programmable logic device. The global clock structure distributes a global clock signal to all portions of the programmable logic device.