Patents Represented by Attorney, Agent or Law Firm Skjerven, Morrill, MacPherson, Franklin and Friel LLP
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Patent number: 6180698Abstract: A liquid chemical formulation suitable for making a thin solid polycarbonate film of highly uniform thickness is formed with polycarbonate material, a liquid that dissolves the polycarbonate, and possibly one or more other constituents. The liquid is typically capable of dissolving the polycarbonate to a concentration of at least 1% at 20° C. and 1 atmosphere. The liquid also typically has a boiling point of at least 80° C. at 1 atmosphere. Examples of the liquid include pyridine, a ring-substituted pyridine derivative, pyrrole, a ring-substituted pyrrole derivative, pyrrolidine, a pyrrolidine derivative, and cyclohexanone. In forming the polycarbonate-containing film, a liquid film (36A) of the liquid chemical formulation is formed over a substructure (30). The liquid film is processed to largely remove the liquid and convert the polycarbonate into a solid film (38).Type: GrantFiled: February 28, 1997Date of Patent: January 30, 2001Assignees: Candescent Technologies Corporation, Hewlett-Packard CompanyInventors: John D. Porter, Scott J. Crane, Stephanie J. Oberg, Anthony W. Johnson
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Patent number: 6118279Abstract: A probability analysis technique is performed on magnetically obtained current data to detect short circuit defects in a plate structure (10) in which a group of first electrical conductors (32) are nominally electrically insulated from and cross a group of second electrical conductors (48). In particular, a magnetic current-sensing operation is performed on at least part of the conductors to produce current data indicative of how much, if any, current flows through each of at least part of the conductors. A short circuit defect probability analysis is then applied to the current data in order to select a location where one of the first conductors crosses one of the second conductors as being most probable of having a short circuit defect.Type: GrantFiled: July 30, 1997Date of Patent: September 12, 2000Assignee: Candescent Technologies CorporationInventors: John E. Field, Stephanie J. Oberg
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Patent number: 6117705Abstract: A package for an integrated circuit is described, as are methods of making the package. The package includes a substrate having a generally planar first surface on which a metal die pad is formed. An integrated circuit die is attached to the metal die pad. An adhesive head surrounds the integrated circuit die and covers the exposed periphery of the metal die pad. A generally planar lid is in a press-fitted interconnection with the bead. An adhesive material covers conductive structures on the die, such as bonding pads, to prevent corrosion. Optionally, the package has vertical peripheral sides. The methods of making the package include methods for making packages individually, or making a plurality of packages simultaneously. Where a plurality of packages are made simultaneously, integrated circuit die are placed on each of a plurality of physically-joined package substrates on a generally planar sheet of substrate material. An adhesive bead is applied around each die.Type: GrantFiled: March 30, 1998Date of Patent: September 12, 2000Assignee: Amkor Technology, Inc.Inventors: Thomas P. Glenn, Roy D. Hollaway, Anthony E. Panczak
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Patent number: 6091111Abstract: A high voltage MOS device includes a P-type substrate having an N-type buried layer formed therein. An N-type epitaxial layer overlies the substrate and a P-type well is formed in the epitaxial layer. A source region is formed in the well such that the source region is directly in contact with the well. No intermediate layer is disposed between the source region and the well. A drain region includes an extended drain region. The extended drain region, which is formed within and in contact with the well, comprises different dopant species and has a maximum dopant concentration of 3.5.times.10.sup.17 cm.sup.-3. A heavily doped main drain region is formed within and in contact with the extended drain region. The source region and extended drain region define a channel region therebetween in the well. An insulator is on a surface of the well over the channel region. A gate is over the insulator.Type: GrantFiled: September 19, 1996Date of Patent: July 18, 2000Assignee: National Semiconductor CorporationInventors: Esin Kutlu Demirlioglu, Monir H. El-Diwany
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Patent number: 6062712Abstract: A lighting fitting for an incandescent lighting arrangement with a pair of incandescent bulbs, includes a lampshade body and a mounting bracket. The lampshade body is formed from molding plastics, and has an upper wall that defines a central through hole, and a skirt portion that extends downwardly and divergently from the periphery defining the upper wall. The mounting bracket includes an elongated middle portion which is formed with a mounting hole aligned with the through hole, and which has a distal wide surface and a proximate wide surface relative to the upper wall, and first and second end portions which are in line with and disposed at opposite ends of the middle portion. The first and second end portions are bent to an acute angle relative to and toward the distal wide surface of the middle portion along two parallel lines which incline at a predetermined angle relative to a vertical line that crosses a longitudinal direction of the middle portion so as to form first and second anchoring surfaces.Type: GrantFiled: July 28, 1999Date of Patent: May 16, 2000Inventor: Duan-Cheng Hsieh
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Patent number: 6045433Abstract: An optical system is disclosed for the inspection of wafers during polishing which also includes a measurement system for measuring the thickness of the wafer's top layer. The optical system views the wafer through a window and includes a gripping system, which places the wafer in a predetermined viewing location while maintaining the patterned surface completely under water. The optical system also includes a pull-down unit for pulling the measurement system slightly below the horizontal prior to the measurement and returns the measuring system to the horizontal afterwards.Type: GrantFiled: June 29, 1995Date of Patent: April 4, 2000Assignee: Nova Measuring Instruments, Ltd.Inventors: Eran Dvir, Eli Haimovich, Benjamin Shulman
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Patent number: 6047032Abstract: In a digital communication system, analog equalization and data recovery are provided with non-linear digital feedback at the receiver, to overcome frequency domain distortion imposed by the communications channel. Digital information from the clock and data recovery circuit is non-linearly filtered and then fed back so as to modulate the threshold of a slicer which receives the signal which has been analog equalized. Thereby any shortcomings in the equalization, slicer, or clock and data recovery are overcome by adjusting the slicer threshold at each clock cycle in response to the recovered clock and data signals.Type: GrantFiled: November 7, 1997Date of Patent: April 4, 2000Assignee: Integrated Circuit Systems, Inc.Inventors: Anthony E. Zortea, Todd A. Wey
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Patent number: 6040946Abstract: Low-cost complex plastic optics allow biocular viewing of video images generated by a single electro-optic display device, such as in a head-mounted display (HMD) for commercial or medical viewing applications. A dual off-axis configuration uses nearly collimated illumination optics and intermediate imaging optics to fill both eyepieces from a single display device without the need for a beamsplitter. Multiple illumination schemes are provided for either monochrome or color, and in either two-dimensional or time-sequential true stereographic presentation. Light from multicolor sources is superimposed, mixed, and homogenized by mixing light cones with diffractive collectors. Offsetting color overcorrection and undercorrection of individual optical elements achieves overall chromatic correction with minimal optical element complexity; A wireless video signal interface eliminates excess cabling.Type: GrantFiled: July 27, 1999Date of Patent: March 21, 2000Assignee: Optimize IncorporatedInventor: Raymond T. Hebert
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Patent number: 6009014Abstract: The present invention provides a method of verifying that all flash EEPROM transistors in a NAND string are properly erased without overerasing by applying a bias voltage to the source of the bottom select gate of the NAND array and applying a non-negative erase verify voltage to the control gates of each transistor during an erase verify. The bias voltage is at least equal to the erased threshold voltage of the worst case transistor to ensure proper erase verification. If all transistors are not erased, then another erase operation is performed. Erasing is repeated until the erase verify operation indicates that all transistors are properly erased. By erasing and verifying according to the present invention, the NAND array is completely and properly erased while minimizing overerasing the array.Type: GrantFiled: June 3, 1998Date of Patent: December 28, 1999Assignee: Advanced Micro Devices, Inc.Inventors: Shane C. Hollmer, Chung-You Hu, Binh Q. Le, Pau-ling Chen, Jonathan Su, Ravi Gutala, Colin Bill
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Patent number: 5915915Abstract: A robotic end effector for loading and unloading a magnetic information storage circular disk on a grinder or polisher carrier surface includes an effector block, an annular vacuum cup, including vacuum apertures, attached to and extending from the block and a vacuum source for attaching the cup to the disk. The cup surrounds and abuts against a periphery of a central aperture of the disk. A bore in the block conveys pressurized air through the cup axial interior, through the disk central aperture to overcome surface tension (stiction) between the carrier surface or platen of the grinder or polisher and the disk underside during unloading. A disk-carrying effector is aligned by including a lens surrounded by a ring of light-emitting diodes directed to fiducial holes on the carrier surface providing for a comparative reflection of light from the diodes by dark holes and a light colored carrier surface.Type: GrantFiled: March 7, 1996Date of Patent: June 29, 1999Assignee: Komag, IncorporatedInventors: Ronald Allen, Peter S. Bae, Kenneth D. Fukui, Gen E. Oshiro
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Patent number: 5897355Abstract: An insulated gate field effect transistor is manufactured according to a process in which an insulated gate structure is formed along a semiconductor chip. Dopant is introduced into the chip to form a body region, semiconductor material outside the body region forming a drain region. Dopant is introduced into the chip at the location of part of the body region to form a source region spaced apart from the drain region by a channel region. Dopant of the same conductivity type as the body-region dopant is introduced through a dopant-introducing section of the chip's upper surface and into the chip at the location of part of the body region to form a sub-surface peaked portion of the body region, the dopant-introducing section being spaced laterally apart from the channel and source regions. The sub-surface peaked portion reaches a peak net dopant concentration below the chip's upper surface so as to improve the transistor's ruggedness under drain avalanche conditions.Type: GrantFiled: October 16, 1997Date of Patent: April 27, 1999Assignee: National Semiconductor CorporationInventors: Constantin Bulucea, Richard A. Blanchard
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Patent number: 5896417Abstract: An electronic apparatus capable of transmitting data at two or more different data rates contains transmitter circuitry, a cable connection mechanism, and an isolation transformer having a primary winding and a secondary winding. The transmitter circuitry low-pass filters digital data which the transmitter circuitry transmits to the primary winding at a first data rate. The transmitter circuitry also transmits digital data to the primary winding at a second data rate different from, typically greater than, the first data rate. The cable connection mechanism provides outgoing data from the secondary winding to the communication cable. Importantly, the transmitter circuitry is operable to generate current-sourced data signals at both data rates and then to convert the current-sourced signals into impedance-produced voltage signals that constitute the outgoing data. Current-source amplifier circuitry normally generates the current-sourced signals.Type: GrantFiled: October 25, 1996Date of Patent: April 20, 1999Assignee: National Semiconductor CorporationInventor: Hung-Wah Anthony Lau
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Patent number: 5877553Abstract: In a packaging arrangement suitable for semiconductor devices, a semiconductor chip is mounted on a surface of an aluminum base with a bonding layer interposed therebetween. The aluminum base has a capability to favorably dissipate heat from the semiconductor chip. The bonding layer consists of a resilient and heat conductive material such as silicone resin mixed with silver powder so that thermal strain of the metal base is accommodated by the resiliency of the bonding layer, and is prevented from adversely affecting the electronic component chip even though the aluminum base demonstrates a substantially more significant thermal expansion than the semiconductor chip. It is therefore possible to achieve a high reliability in the packaging of semiconductor devices at a minimum cost.Type: GrantFiled: October 31, 1996Date of Patent: March 2, 1999Assignee: NHK Spring Co., Ltd.Inventors: Osamu Nakayama, Koji Ishikawa
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Patent number: 5866939Abstract: The invention relates to a grid array type lead frame having a plurality of leads classified into groups by length forming a lead end grid array semiconductor package. The leads extend to respective lead ends, in each of which at least one different plane direction-converting lead part and/or at least one identical plane direction-converting lead part is formed by at least one bending part, whereby the lead ends are distributed in a grid array. The invention includes a lead end grid array semiconductor package employing the grid array type lead frame, which is as small as or similar to that of semiconductor chip in area while the lead ends are arrayed on one plane, farther distant way from neighboring ones but in a higher number per area, in such a manner that they form a grid array.Type: GrantFiled: December 31, 1996Date of Patent: February 2, 1999Assignees: Anam Semiconductor Inc., Amkor Technology, Inc.Inventors: Won Sun Shin, Byung Joon Han, Ju Hoon Yoon, Sung Bum Kwak, In Gyu Han
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Patent number: 5864470Abstract: A flexible circuit board for a ball grid array semiconductor package including a flexible resin film, a plurality of electrically conductive traces formed on an upper surface of the resin film, the conductive traces having solder ball pads, and a die flag including a semiconductor chip paddle located on a central portion of the circuit board, the chip paddle having a plurality of heat-discharging and grounding solder ball pads, and a plurality of lattice-shaped traces adapted to electrically connect the solder ball pads, the traces being shaped into a lattice to prevent a bleed-out of a silver-filled epoxy resin, a ground bonding rim located around the chip paddle, and a plurality of radial traces adapted to electrically connect the chip paddle to the ground bonding rim, and the flexible resin film being perforated to define solder ball lands on lower surfaces of the solder ball pads.Type: GrantFiled: June 25, 1997Date of Patent: January 26, 1999Assignees: Anam Semiconductor Inc., Amkor Technology, Inc.Inventors: Il Kwon Shim, Young Wook Heo, Robert Francis Darveaux
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Patent number: 5864817Abstract: An MPEG audio/video decoder has memories, a signal processing unit (SPU) including a multiplier and a butterfly unit, a main CPU, and a memory controller which are time division multiplexed between decoding video and audio data. For audio decoding, the butterfly unit determines combinations of components of a frequency-domain vector to reduce the number of multiplies required to transform to the time domain (matrixing). Matrixing is interwoven with MPEG filtering to increase throughput of the decoder by increasing parallel use of the multiplier, the butterfly unit, and a memory controller.Type: GrantFiled: October 26, 1995Date of Patent: January 26, 1999Assignee: C-Cube Microsystems Inc.Inventor: David E. Galbi
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Patent number: 5862076Abstract: Each read line in a memory array containing a plurality of alternating bit lines and read lines with columns of memory cells therebetween, is broken into a plurality of electrically isolatable segments. As a result, the capacitance associated with each read line is significantly reduced and the speed of reading information from or writing information into a memory cell is significantly increased while at the same time not decreasing the density of the array.Type: GrantFiled: June 30, 1992Date of Patent: January 19, 1999Assignee: WaferScale Integration, Inc.Inventor: Boaz Eitan
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Patent number: 5852870Abstract: A grid array assembly method uses a semi-flexible substrate printed circuit board and includes steps of providing a series of conforming boards each board including bonding pads and metallization on a first surface and conductive vias in the board extending to a second opposite surface containing a contact pad array, testing the boards and determining acceptable boards. A carrier strip with longitudinally aligned apertures mounts individual accepted boards. The strip with mounted boards is passed to a station where an IC die is mounted on the board first surface, wire bonds are placed from the die to the bonding pads and the assembly encapsulated by automolding against a board first surface portion using the strip as the mold gate to form a package body. Subsequently interconnecting balls or bumps are placed on the contact pads and the assembly is removed from the strip.Type: GrantFiled: April 24, 1996Date of Patent: December 29, 1998Assignee: Amkor Technology, Inc.Inventors: Bruce J. Freyman, John Briar, Jack C. Maxcy
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Patent number: 5832131Abstract: A hashing-based vector quantization process partitions a codebook into buckets. A hashing function determines the locations of buckets in the codebook and is selected so that buckets containing similar codevectors start near each other in the codebook. One hashing function forms an index from the most significant bits of components of a vector. During encoding, the hashing function generates an index from an input vector, and a search for a codevector matching the image vector begins in a bucket indicated by the index. In one embodiment, the codebook contains flag fields to indicate the starts of buckets and pointer fields to create linked lists of codevectors which form the buckets. Codevectors are compared to the input vector by determining the mean squared error of the difference between the codevector and the input vector. A search is complete when the search finds a codevector having a difference with a MSE less than a threshold.Type: GrantFiled: May 3, 1995Date of Patent: November 3, 1998Assignee: National Semiconductor CorporationInventors: Chang Y. Choo, Xiaonong Ran
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Patent number: D438179Type: GrantFiled: May 25, 1999Date of Patent: February 27, 2001Inventor: Chi Wang-Tsai