Abstract: A multi-tasking, dynamically controlled micro-sequencer for use in a TDMA communication system is described. Rather than the output of the sequencer being solely a linear sequence of instructions in a microcode RAM, the output of the sequencer is augmented by an output of finite state machines (FSMs) providing a sequence of control codes. The FSMs provide control signals for building a slot in accordance with a specific protocol. The sequencer core provides enabling signals to the FSMs to enable the proper FSM depending upon the mode of the transceiver. A conditional logic block is included in the sequencer core which detects special operation codes (opcodes) for each slot to cause the microcode sequence to jump to a certain routine if a condition is met or not met.

Abstract: A general purpose architecture for a digital microcomputer, which includes a central processing unit, random access memory, user-defined dedicated functions and an optional programmable read only memory. Instructions are fetched either externally or from the optionally ROM. Data can be fetched externally or internally. Each instruction fetched is interpreted by a general-purpose microengine. The architecture is flexible enough to permit the modular addition, deletion and modification of dedicated functions and microinstructions (including changes in execution timing and decoding), as well as the testing of memory independently from the rest of the architecture.