Patents Represented by Attorney, Agent or Law Firm Skjerven Morrill MacPherson LLP
  • Patent number: 6871261
    Abstract: A dynamic random access memory integrated circuit and method includes internal refresh control and an array configured to receive read and write access requests having priority over pending refresh requests, wherein refresh requests are queueable and retired on clock cycles not requiring an access of the array and complete in one clock cycle. No onboard cache memory is required. A method includes: determining within the circuit when one of the banks of the array requires a refresh, prioritizing read and write access requests over pending refresh requests, read access requests initiating an access to the array without determining whether data is available from outside the array, and retiring within a clock cycle one pending refresh request to a bank when that bank has pending refresh requests and does not also require an access of the array on that clock cycle.
    Type: Grant
    Filed: November 15, 2001
    Date of Patent: March 22, 2005
    Assignee: Integrated Device Technology, Inc.
    Inventor: Robert J. Proebsting
  • Patent number: 6580639
    Abstract: The present invention makes use of ion bombardment to amorphize the source and drain regions of a short channel FET prior to implanting. The source/drain implants are then localized to a shallow depth by appropriate choice of implanting conditions, typically employing rather low bombardment voltages of approximately 10 KeV. Amorphous source/drain regions substantially hinder the diffusion of source/drain dopants and thereby reduce the possibility of punchthrough and loss of FET function. Such devices are preferably used in NAND type flash memory devices maintaining proper self-boosting voltages and FET functions even when short channel lengths are employed.
    Type: Grant
    Filed: August 10, 1999
    Date of Patent: June 17, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Yue-Song He, Kent Kuohua Chang, Allen U. Huang
  • Patent number: 6576976
    Abstract: A first insulating layer (12) overlying semiconductor substrate (10) has a plurality of conductive paths (14, 16) disposed thereon. Each of the plurality of conductive paths has at least a major portion thereof overlied with a second insulating layer (20). A third insulating layer (26), having air gap ports (28) formed therein, overlies adjacent conductive paths and extends from one to another such that an air gap (34) is formed. A passivation layer (30) overlies third insulating layer and seals the plurality of air gaps ports to form an insulation structure (40) for a semiconductor integrated circuit, and method thereof.
    Type: Grant
    Filed: February 22, 2001
    Date of Patent: June 10, 2003
    Assignee: Integrated Device Technology, Inc.
    Inventors: Chuen-Der Lien, S. K. Lee
  • Patent number: 6531975
    Abstract: An apparatus and method for converting digital input signals sampled at different rates to analog signals includes a digital to analog converter for each digital input signal. Each digital to analog converter receives a digital input signal and a clock signal corresponding to the sampling rate of the received digital input signal. The apparatus can also receive a set of sample rate signals indicating the sampling rate for each digital input signal. The sample rate signals are used to route each digital input signal, along with a corresponding clock signal, to a corresponding digital to analog converter (DAC). A clock error signal controls routing of the digital input signals to the DACs as well as operation of the DACs. A clock divider and ratio detector module generates the clock error signal based on intermediate clock error signals that correspond to the sample rates.
    Type: Grant
    Filed: May 24, 2001
    Date of Patent: March 11, 2003
    Assignee: Cirrus Logic, Incorporated
    Inventors: Brian D. Trotter, Thomas D. Stein, Heling Yi, Jason P. Rhode, Timothy T. Rueger
  • Patent number: 6529423
    Abstract: An internal clock delay circuit of a semiconductor device and a method for delaying an internal clock of the semiconductor device. The semiconductor device includes a CAS latency signal generator that generates CAS latency signals comprising a first CAS latency signal, a second CAS latency signal and a third CAS latency signal, and an internal clock delay circuit that receives one of the CAS latency signals and an internal clock signal and delays the internal clock signal by a predetermined time in response to the received CAS latency signal. The internal clock delay circuit includes delay circuits that delay the internal clock signal, and the internal clock signal passes through only one among the delay circuits when the semiconductor device operates in the second CAS latency mode.
    Type: Grant
    Filed: February 22, 2000
    Date of Patent: March 4, 2003
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sei-seung Yoon, Sang-pyo Hong
  • Patent number: 6504301
    Abstract: An LED package and a method of fabricating the LED package utilize a prefabricated fluorescent member that contains a fluorescent material that can be separately tested for optical properties before assembly to ensure the proper performance of the LED package with respect to the color of the output light. The LED package includes one or more LED dies that operate as the light source of the package. Preferably, the fluorescent material included in the prefabricated fluorescent member and the LED dies of the LED package are selectively chosen, so that output light generated by the LED package duplicates natural white light. In a first embodiment of the invention, the prefabricated fluorescent member is a substantially planar plate having a disk-like shape. In a second embodiment, the prefabricated fluorescent member is a non-planar disk that conforms to and is attached to the inner surface of a concave lens.
    Type: Grant
    Filed: September 3, 1999
    Date of Patent: January 7, 2003
    Assignee: LumiLeds Lighting, U.S., LLC
    Inventor: Christopher H. Lowery
  • Patent number: 6461932
    Abstract: A trenched-isolated semiconductor structure is created by a process that entails forming a patterned trench (54) along an upper surface of a semiconductor body (40). A dielectric layer (56) is provided over the upper semiconductor surface. The dielectric layer is covered with a smoothening layer (60) whose upper surface is smoother than the upper surface of the dielectric layer. The smoothening layer is removed starting from its upper surface. During the removal of the smoothening layer, upward-protruding material of the dielectric layer progressively becomes exposed and is also removed. As a result, the remainder of dielectric layer has a smoother upper surface than the initial upper surface of the dielectric layer.
    Type: Grant
    Filed: December 14, 1998
    Date of Patent: October 8, 2002
    Assignee: National Semiconductor Corporation
    Inventor: Fu-Cheng Wang
  • Patent number: 6450573
    Abstract: Provided is a vehicle seat device equipped with an anti-submarine vehicle seat device for preventing submarine at the time of an impact without increasing the size and weight of the seat assembly. The casing and/or the restraint member serve the dual purposes as structural members for the seat frame so that the overall amount of the material for the structural members can be reduced.
    Type: Grant
    Filed: March 15, 2000
    Date of Patent: September 17, 2002
    Assignee: NHK Spring Co., Ltd.
    Inventors: Hiroyoshi Yamaguchi, Hajime Shono
  • Patent number: 6452440
    Abstract: A charge pump system includes a charge pumping circuit for outputting a high voltage VPP at a node. An oscillator circuit, coupled to the charge pumping circuit, drives the charge pumping circuit with at least one clock signal. A current source generates a pulldown current. A voltage divider circuit is coupled between the node and the current source. The voltage divider circuit cooperates with the current source to form a feedback loop for controlling the oscillator circuit to run at variable, optimum frequency for controlling the rate-of-rise and the amplitude of the high voltage VPP while minimizing power-supply current drain.
    Type: Grant
    Filed: January 10, 2001
    Date of Patent: September 17, 2002
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Karl Rapp
  • Patent number: 6446164
    Abstract: A circuit and method for reading and writing to a microprocessor's internal cache memory during a test mode of operation. During write accesses, an external data bus transmits to an internal data bus an address, cache tags and data in accordance with an external clock. During read accesses, the external data bus transmits an address and receives from the internal data bus data and cache tags. In one embodiment, during a write access, the external data bus is time-multiplexed to transmit an address, cache tags and data in two clock periods of the external clock the external data bus is time-multiplexed to transmit to the internal data bus an address in the first clock period of the external clock signal and to receive tag and data in the next successive clock periods of the external clock signal. In this embodiment, reserved pins are used to specify a cache access mode, including a test mode of operation.
    Type: Grant
    Filed: March 14, 1997
    Date of Patent: September 3, 2002
    Assignee: Integrated Device Technology, Inc.
    Inventors: De H. Nguyen, Raymond M. Chu
  • Patent number: 6441687
    Abstract: A novel bias voltage generating circuit and method are disclosed. In one embodiment, the bias voltage generating circuit includes a first transistor with a base terminal coupled to the output node and an emitter terminal coupled to ground. The circuit also includes a resistor with a first terminal coupled to a supply voltage node and a second terminal coupled to a collector terminal of the first transistor. A second transistor has an emitter terminal coupled to the collector terminal of the first transistor and a base terminal connected to the collector terminal of the second transistor. A second resistance has a first terminal coupled to the supply voltage node and a second terminal coupled to a collector terminal of the second transistor. A third transistor has a base terminal coupled to the base terminal of the second transistor, a collector terminal coupled to the supply voltage node, and an emitter terminal coupled to the output node.
    Type: Grant
    Filed: August 29, 2000
    Date of Patent: August 27, 2002
    Assignee: TriQuint Semiconductor, Inc.
    Inventor: Thomas R. Apel
  • Patent number: 6439552
    Abstract: The overhead wire tensioning device of the present invention is improved in reliability and eliminates the need for constant maintenance work by protecting the slide mechanism between the cylinder case of the gas spring type overhead wire tensioning device and the cylinder rod, and the pivoting mechanism for the connecting rod connecting this cylinder with the overhead wire from external influences.
    Type: Grant
    Filed: November 3, 1999
    Date of Patent: August 27, 2002
    Assignees: Central Japan Railway Company, Dengyo Incorporated, NHK Spring Co., Ltd.
    Inventors: Satoshi Ageishi, Hiroshi Amano, Yoshio Narumiya, Toru Uchikoshi, Shoji Konta, Yoshinori Wakabayashi, Takeyoshi Shinbori, Takeshi Uchida
  • Patent number: 6441651
    Abstract: An input buffer for use in an integrated circuit having a VCC voltage supply and a VSS voltage supply. The input buffer includes a p-channel field effect transistor (FET) having a source region coupled to the VCC voltage supply, a drain region coupled to a bias circuit, and a gate electrode coupled to an input terminal. The bias circuit maintains a voltage at the drain region of the p-channel FET which is slightly greater than the VSS supply voltage when a logic high voltage is applied to the input terminal. In an alternate embodiment, the input buffer includes an n-channel FET having a drain region coupled to the VCC voltage supply, a source region coupled to the output terminal and a gate electrode coupled to the input terminal. The bias circuit maintains a voltage at the source of the n-channel FET which is greater than the VSS supply voltage when a logic low voltage is applied to the input terminal.
    Type: Grant
    Filed: February 14, 2000
    Date of Patent: August 27, 2002
    Assignee: Integrated Device Technology, Inc.
    Inventor: Chuen-Der Lien
  • Patent number: 6438223
    Abstract: One-Number-Service (ONS) allows a subscriber to keep a single Directory Number when relocating to a different access point among one or more interconnected telecommunication systems. According to one aspect of the invention, a signaling packet for a call setup to a ported number is intercepted at an improved signal transfer point where a query to a database returns a new address of the exchange the number has ported to. The new address is used to update the signaling packet at the improved signal transfer point in order to set up the call to the ported exchange. According to another aspect of the invention, an improved exchange triggers to do a query to obtain the new address of the exchange the number has ported to. The new address is used to update the signaling packet at the exchange in order to set up the call to the ported exchange. Yet other aspects of the invention include combination of query and signaling packet processing at the signal transfer point and the exchange.
    Type: Grant
    Filed: March 3, 1999
    Date of Patent: August 20, 2002
    Assignee: Open Telephone Network, Inc.
    Inventors: Farokh H. Eskafi, Mohammad D. Kazerouni
  • Patent number: 6428124
    Abstract: A health care test kiosk includes a carrel body that supports a console housing and has a vacant knee-space beneath the console housing. The carrel body includes a support side panel forming a lateral side and extending beyond the console housing and the knee-space. A physiological test interface is connected to and supported by the carrel body on the support side panel. A retractable seat is movably connected to the support side panel of the carrel body for selective positioning in a location ranging from withdrawn into the knee-space beneath the console housing to extended completely from the knee-space.
    Type: Grant
    Filed: April 14, 2000
    Date of Patent: August 6, 2002
    Assignee: Computerized Screening, Inc.
    Inventors: Charles Bluth, James Bluth, Raymond G. Bryan, Jim C. Lovell
  • Patent number: 6428531
    Abstract: Partial or total occlusions of fluid passages within the human body are removed by positioning an array of optical fibers in the passage and directing treatment radiation pulses along the fibers, one at a time, to generate a shock wave and hydrodynamics flows that strike and emulsify the occlusions. A preferred application is the removal of blood clots (thrombin and embolic) from small cerebral vessels to reverse the effects of an ischemic stroke. The operating parameters and techniques are chosen to minimize the amount of heating of the fragile cerebral vessel walls occurring during this photo acoustic treatment. One such technique is the optical monitoring of the existence of hydrodynamics flow generating vapor bubbles when they are expected to occur and stopping the heat generating pulses propagated along an optical fiber that is not generating such bubbles.
    Type: Grant
    Filed: June 27, 2000
    Date of Patent: August 6, 2002
    Assignees: The Regents of the University of California, Endovasix, Inc.
    Inventors: Steven R. Visuri, Luiz B. Da Silva, Peter M. Celliers, Richard A. London, Duncan J. Maitland, IV, Victor C. Esch
  • Patent number: 6427226
    Abstract: Tools and techniques used in conjunction with integrated circuit path timing information can selectively reduce the channel length of transistors in cells associated with the most critical paths in an integrated circuit, while keeping the overall integrated circuit design within a specified power budget. Moreover, by targeting pins of cells (and thus their associated transistors) that are used by multiple paths, and/or that offer the greatest potential speed improvement, timing violations along critical paths can be reduced or eliminated with a relatively few number of replacements. Paths within a certain timing violation range are selected for analysis. The pins within those paths are ranked by pin criticality, which can depend on, for example, the number of times a particular pin occurs in any path, the timing enhancement associated with replacing a cell having that pin, and the impact of replacing a cell having that pin would have on the power budget.
    Type: Grant
    Filed: May 25, 1999
    Date of Patent: July 30, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Dhiraj Mallick, Jacob Thomas, Rajesh Khanna, Anil L. Pandya, Satish Kumar Raj
  • Patent number: 6423612
    Abstract: A shallow trench isolation (STI) region is covered with a nitride layer. The nitride layer, advantageously, fills in gaps in the underlying dielectric layer, such as seams, thereby reducing leakage. The nitride layer may be patterned to form a spacer above the STI region which is used to define an opening in the polysilicon layer that is subsequently deposited. The polysilicon layer is etched back to expose the nitride spacer, which is then etched away in a controlled fashion. Thus, a small opening may be formed in the polysilicon layer. Further, because the polysilicon layer is etched back to the top of the nitride spacer, the polysilicon layer is planarized thereby reducing stringers in subsequent processing.
    Type: Grant
    Filed: June 26, 2000
    Date of Patent: July 23, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Wenge Yang, John Jianshi Wang, Fei Wang
  • Patent number: 6424209
    Abstract: A programmable capacitor array including a plurality of user-selectable, numerically weighted capacitors, each of which includes at least one fixed capacitor and one manufacturer-controlled trim capacitor, advantageously provides a variety of selectable capacitance values for a programmable analog integrated circuit. When coupled to a memory, for example a static memory, switches can be controlled that determine whether a particular fixed capacitor (user-selectable) or trim capacitor (manufacturer-selectable) is electrically coupled into the circuit. User access to those portions of memory controlling switches associated with the trim capacitors can be restricted via an I/O interface and security command. Such programmable capacitor arrays allow efficient implementation of user-programmable filter circuits where the user can conveniently program or reprogram a variety of filter parameters.
    Type: Grant
    Filed: February 18, 2000
    Date of Patent: July 23, 2002
    Assignee: Lattice Semiconductor Corporation
    Inventors: James L. Gorecki, Yaohua Yang
  • Patent number: 6424384
    Abstract: A method and apparatus for separating a signal uses a low pass filtering in a first direction to produce a signal with a low component and a alias component and then uses a filtering in a second direction to produce a component of a separated signal. The filter has applications in television signal decoding and has other applications.
    Type: Grant
    Filed: July 22, 1999
    Date of Patent: July 23, 2002
    Assignee: Zilog, Inc.
    Inventor: Anatoliy V. Tsyrganovich