Patents Represented by Attorney, Agent or Law Firm Skjerven Morrill MacPherson LLP
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Patent number: 6580639Abstract: The present invention makes use of ion bombardment to amorphize the source and drain regions of a short channel FET prior to implanting. The source/drain implants are then localized to a shallow depth by appropriate choice of implanting conditions, typically employing rather low bombardment voltages of approximately 10 KeV. Amorphous source/drain regions substantially hinder the diffusion of source/drain dopants and thereby reduce the possibility of punchthrough and loss of FET function. Such devices are preferably used in NAND type flash memory devices maintaining proper self-boosting voltages and FET functions even when short channel lengths are employed.Type: GrantFiled: August 10, 1999Date of Patent: June 17, 2003Assignee: Advanced Micro Devices, Inc.Inventors: Yue-Song He, Kent Kuohua Chang, Allen U. Huang
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Patent number: 6529423Abstract: An internal clock delay circuit of a semiconductor device and a method for delaying an internal clock of the semiconductor device. The semiconductor device includes a CAS latency signal generator that generates CAS latency signals comprising a first CAS latency signal, a second CAS latency signal and a third CAS latency signal, and an internal clock delay circuit that receives one of the CAS latency signals and an internal clock signal and delays the internal clock signal by a predetermined time in response to the received CAS latency signal. The internal clock delay circuit includes delay circuits that delay the internal clock signal, and the internal clock signal passes through only one among the delay circuits when the semiconductor device operates in the second CAS latency mode.Type: GrantFiled: February 22, 2000Date of Patent: March 4, 2003Assignee: Samsung Electronics Co., Ltd.Inventors: Sei-seung Yoon, Sang-pyo Hong
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Patent number: 6504301Abstract: An LED package and a method of fabricating the LED package utilize a prefabricated fluorescent member that contains a fluorescent material that can be separately tested for optical properties before assembly to ensure the proper performance of the LED package with respect to the color of the output light. The LED package includes one or more LED dies that operate as the light source of the package. Preferably, the fluorescent material included in the prefabricated fluorescent member and the LED dies of the LED package are selectively chosen, so that output light generated by the LED package duplicates natural white light. In a first embodiment of the invention, the prefabricated fluorescent member is a substantially planar plate having a disk-like shape. In a second embodiment, the prefabricated fluorescent member is a non-planar disk that conforms to and is attached to the inner surface of a concave lens.Type: GrantFiled: September 3, 1999Date of Patent: January 7, 2003Assignee: LumiLeds Lighting, U.S., LLCInventor: Christopher H. Lowery
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Patent number: 6461932Abstract: A trenched-isolated semiconductor structure is created by a process that entails forming a patterned trench (54) along an upper surface of a semiconductor body (40). A dielectric layer (56) is provided over the upper semiconductor surface. The dielectric layer is covered with a smoothening layer (60) whose upper surface is smoother than the upper surface of the dielectric layer. The smoothening layer is removed starting from its upper surface. During the removal of the smoothening layer, upward-protruding material of the dielectric layer progressively becomes exposed and is also removed. As a result, the remainder of dielectric layer has a smoother upper surface than the initial upper surface of the dielectric layer.Type: GrantFiled: December 14, 1998Date of Patent: October 8, 2002Assignee: National Semiconductor CorporationInventor: Fu-Cheng Wang
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Patent number: 6452440Abstract: A charge pump system includes a charge pumping circuit for outputting a high voltage VPP at a node. An oscillator circuit, coupled to the charge pumping circuit, drives the charge pumping circuit with at least one clock signal. A current source generates a pulldown current. A voltage divider circuit is coupled between the node and the current source. The voltage divider circuit cooperates with the current source to form a feedback loop for controlling the oscillator circuit to run at variable, optimum frequency for controlling the rate-of-rise and the amplitude of the high voltage VPP while minimizing power-supply current drain.Type: GrantFiled: January 10, 2001Date of Patent: September 17, 2002Assignee: Fairchild Semiconductor CorporationInventor: Karl Rapp
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Patent number: 6450573Abstract: Provided is a vehicle seat device equipped with an anti-submarine vehicle seat device for preventing submarine at the time of an impact without increasing the size and weight of the seat assembly. The casing and/or the restraint member serve the dual purposes as structural members for the seat frame so that the overall amount of the material for the structural members can be reduced.Type: GrantFiled: March 15, 2000Date of Patent: September 17, 2002Assignee: NHK Spring Co., Ltd.Inventors: Hiroyoshi Yamaguchi, Hajime Shono
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Patent number: 6446164Abstract: A circuit and method for reading and writing to a microprocessor's internal cache memory during a test mode of operation. During write accesses, an external data bus transmits to an internal data bus an address, cache tags and data in accordance with an external clock. During read accesses, the external data bus transmits an address and receives from the internal data bus data and cache tags. In one embodiment, during a write access, the external data bus is time-multiplexed to transmit an address, cache tags and data in two clock periods of the external clock the external data bus is time-multiplexed to transmit to the internal data bus an address in the first clock period of the external clock signal and to receive tag and data in the next successive clock periods of the external clock signal. In this embodiment, reserved pins are used to specify a cache access mode, including a test mode of operation.Type: GrantFiled: March 14, 1997Date of Patent: September 3, 2002Assignee: Integrated Device Technology, Inc.Inventors: De H. Nguyen, Raymond M. Chu
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Patent number: 6441687Abstract: A novel bias voltage generating circuit and method are disclosed. In one embodiment, the bias voltage generating circuit includes a first transistor with a base terminal coupled to the output node and an emitter terminal coupled to ground. The circuit also includes a resistor with a first terminal coupled to a supply voltage node and a second terminal coupled to a collector terminal of the first transistor. A second transistor has an emitter terminal coupled to the collector terminal of the first transistor and a base terminal connected to the collector terminal of the second transistor. A second resistance has a first terminal coupled to the supply voltage node and a second terminal coupled to a collector terminal of the second transistor. A third transistor has a base terminal coupled to the base terminal of the second transistor, a collector terminal coupled to the supply voltage node, and an emitter terminal coupled to the output node.Type: GrantFiled: August 29, 2000Date of Patent: August 27, 2002Assignee: TriQuint Semiconductor, Inc.Inventor: Thomas R. Apel
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Patent number: 6439552Abstract: The overhead wire tensioning device of the present invention is improved in reliability and eliminates the need for constant maintenance work by protecting the slide mechanism between the cylinder case of the gas spring type overhead wire tensioning device and the cylinder rod, and the pivoting mechanism for the connecting rod connecting this cylinder with the overhead wire from external influences.Type: GrantFiled: November 3, 1999Date of Patent: August 27, 2002Assignees: Central Japan Railway Company, Dengyo Incorporated, NHK Spring Co., Ltd.Inventors: Satoshi Ageishi, Hiroshi Amano, Yoshio Narumiya, Toru Uchikoshi, Shoji Konta, Yoshinori Wakabayashi, Takeyoshi Shinbori, Takeshi Uchida
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Patent number: 6438223Abstract: One-Number-Service (ONS) allows a subscriber to keep a single Directory Number when relocating to a different access point among one or more interconnected telecommunication systems. According to one aspect of the invention, a signaling packet for a call setup to a ported number is intercepted at an improved signal transfer point where a query to a database returns a new address of the exchange the number has ported to. The new address is used to update the signaling packet at the improved signal transfer point in order to set up the call to the ported exchange. According to another aspect of the invention, an improved exchange triggers to do a query to obtain the new address of the exchange the number has ported to. The new address is used to update the signaling packet at the exchange in order to set up the call to the ported exchange. Yet other aspects of the invention include combination of query and signaling packet processing at the signal transfer point and the exchange.Type: GrantFiled: March 3, 1999Date of Patent: August 20, 2002Assignee: Open Telephone Network, Inc.Inventors: Farokh H. Eskafi, Mohammad D. Kazerouni
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Patent number: 6428124Abstract: A health care test kiosk includes a carrel body that supports a console housing and has a vacant knee-space beneath the console housing. The carrel body includes a support side panel forming a lateral side and extending beyond the console housing and the knee-space. A physiological test interface is connected to and supported by the carrel body on the support side panel. A retractable seat is movably connected to the support side panel of the carrel body for selective positioning in a location ranging from withdrawn into the knee-space beneath the console housing to extended completely from the knee-space.Type: GrantFiled: April 14, 2000Date of Patent: August 6, 2002Assignee: Computerized Screening, Inc.Inventors: Charles Bluth, James Bluth, Raymond G. Bryan, Jim C. Lovell
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Patent number: 6428531Abstract: Partial or total occlusions of fluid passages within the human body are removed by positioning an array of optical fibers in the passage and directing treatment radiation pulses along the fibers, one at a time, to generate a shock wave and hydrodynamics flows that strike and emulsify the occlusions. A preferred application is the removal of blood clots (thrombin and embolic) from small cerebral vessels to reverse the effects of an ischemic stroke. The operating parameters and techniques are chosen to minimize the amount of heating of the fragile cerebral vessel walls occurring during this photo acoustic treatment. One such technique is the optical monitoring of the existence of hydrodynamics flow generating vapor bubbles when they are expected to occur and stopping the heat generating pulses propagated along an optical fiber that is not generating such bubbles.Type: GrantFiled: June 27, 2000Date of Patent: August 6, 2002Assignees: The Regents of the University of California, Endovasix, Inc.Inventors: Steven R. Visuri, Luiz B. Da Silva, Peter M. Celliers, Richard A. London, Duncan J. Maitland, IV, Victor C. Esch
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Patent number: 6427226Abstract: Tools and techniques used in conjunction with integrated circuit path timing information can selectively reduce the channel length of transistors in cells associated with the most critical paths in an integrated circuit, while keeping the overall integrated circuit design within a specified power budget. Moreover, by targeting pins of cells (and thus their associated transistors) that are used by multiple paths, and/or that offer the greatest potential speed improvement, timing violations along critical paths can be reduced or eliminated with a relatively few number of replacements. Paths within a certain timing violation range are selected for analysis. The pins within those paths are ranked by pin criticality, which can depend on, for example, the number of times a particular pin occurs in any path, the timing enhancement associated with replacing a cell having that pin, and the impact of replacing a cell having that pin would have on the power budget.Type: GrantFiled: May 25, 1999Date of Patent: July 30, 2002Assignee: Advanced Micro Devices, Inc.Inventors: Dhiraj Mallick, Jacob Thomas, Rajesh Khanna, Anil L. Pandya, Satish Kumar Raj
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Patent number: 6424209Abstract: A programmable capacitor array including a plurality of user-selectable, numerically weighted capacitors, each of which includes at least one fixed capacitor and one manufacturer-controlled trim capacitor, advantageously provides a variety of selectable capacitance values for a programmable analog integrated circuit. When coupled to a memory, for example a static memory, switches can be controlled that determine whether a particular fixed capacitor (user-selectable) or trim capacitor (manufacturer-selectable) is electrically coupled into the circuit. User access to those portions of memory controlling switches associated with the trim capacitors can be restricted via an I/O interface and security command. Such programmable capacitor arrays allow efficient implementation of user-programmable filter circuits where the user can conveniently program or reprogram a variety of filter parameters.Type: GrantFiled: February 18, 2000Date of Patent: July 23, 2002Assignee: Lattice Semiconductor CorporationInventors: James L. Gorecki, Yaohua Yang
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Patent number: 6424384Abstract: A method and apparatus for separating a signal uses a low pass filtering in a first direction to produce a signal with a low component and a alias component and then uses a filtering in a second direction to produce a component of a separated signal. The filter has applications in television signal decoding and has other applications.Type: GrantFiled: July 22, 1999Date of Patent: July 23, 2002Assignee: Zilog, Inc.Inventor: Anatoliy V. Tsyrganovich
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Patent number: 6424276Abstract: A digital calibration system for an analog-to-digital converter system includes a computational system receiving digital bits from an analog-to-digital converter representing selection of elements of the digital-to-analog converter in response to an analog input. The computational engine produces a digital output representative of the analog input during conversion operation, and digital values for adjustment of an adjustable analog source during calibration. Further, a digital system comprises a radix-less-than-two non-configurable digital-to-analog converter, a comparator system connected to the converter, and a computational system configured for SAR calibration and conversion.Type: GrantFiled: September 9, 1999Date of Patent: July 23, 2002Assignee: Cirrus Logic, Inc.Inventors: Carlos Esteban Muñoz, Karl Ernesto Thompson, Douglas S. Piasecki, Wai Laing Lee, Eric Swanson
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Patent number: 6423612Abstract: A shallow trench isolation (STI) region is covered with a nitride layer. The nitride layer, advantageously, fills in gaps in the underlying dielectric layer, such as seams, thereby reducing leakage. The nitride layer may be patterned to form a spacer above the STI region which is used to define an opening in the polysilicon layer that is subsequently deposited. The polysilicon layer is etched back to expose the nitride spacer, which is then etched away in a controlled fashion. Thus, a small opening may be formed in the polysilicon layer. Further, because the polysilicon layer is etched back to the top of the nitride spacer, the polysilicon layer is planarized thereby reducing stringers in subsequent processing.Type: GrantFiled: June 26, 2000Date of Patent: July 23, 2002Assignee: Advanced Micro Devices, Inc.Inventors: Wenge Yang, John Jianshi Wang, Fei Wang
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Patent number: 6420913Abstract: A driver capable of launching signals into a transmission line and of terminating signals at a receiver end of the transmission line includes within the driver a circuit for controlling the output impedance and a circuit for controlling the output slew rate. Accordingly, a desired output impedance can be advantageously established and maintained over a wide range of variations in operating conditions, manufacturing processes and output voltage levels. Such a driver also advantageously limits any crowbar current, thereby reducing the overall power consumption of the driver with little, if any, degradation of driver performance. The driver includes a pull up circuit coupled to receive at least one of a plurality of control codes. The pull up circuit includes pull up output circuit and an impedance control buffer circuit, a parallel pull up circuit, the parallel pull up circuit and the pull up output circuit being controllable to adjust the impedance of the pull up circuit.Type: GrantFiled: September 20, 1999Date of Patent: July 16, 2002Assignee: Sun Microsystems, Inc.Inventors: Michael A. Ang, Alexander D. Taylor, Jonathan E. Starr, Sai V. Vishwanthaiah
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Quantization using frequency and mean compensated frequency input data for robust speech recognition
Patent number: 6418412Abstract: A speech recognition system utilizes multiple quantizers to process frequency parameters and mean compensated frequency parameters derived from an input signal. The quantizers may be matrix and vector quantizer pairs, and such quantizer pairs may also function as front ends to a second stage speech classifiers such as hidden Markov models (HMMs) and/or utilizes neural network postprocessing to, for example, improve speech recognition performance. Mean compensating the frequency parameters can remove noise frequency components that remain approximately constant during the duration of the input signal. HMM initial state and state transition probabilities derived from common quantizer types and the same input signal may be consolidated to improve recognition system performance and efficiency. Matrix quantization exploits the “evolution” of the speech short-term spectral envelopes as well as frequency domain information, and vector quantization (VQ) primarily operates on frequency domain information.Type: GrantFiled: August 28, 2000Date of Patent: July 9, 2002Assignee: Legerity, Inc.Inventors: Safdar M. Asghar, Lin Cong -
Patent number: 6417848Abstract: A 3-D graphics system combines a software programmed setup processor, a 3-D pipeline, and a software programmed back end processor. The setup processor performs “setup” on polygons for the 3-D pipeline. The 3-D pipeline rasterizes the polygons to create pixels. The back end processor performs back end processing, such as Z-buffering and alpha blending on the pixels. In one embodiment, the throughput of the 3-D graphics system is increased by clusterizing the pixels before back end processing. Specifically, a clusterizer combines pixels into clusters that can be processed by the back end processors without data coherency problems. Furthermore, the pixels are selected for a cluster to minimize memory latency and access times. In some embodiments, clusters are filled with fill addresses by a cluster filler. The filled addresses generated by the cluster filler, do not cause potential hazards in the back end processor.Type: GrantFiled: August 25, 1997Date of Patent: July 9, 2002Assignee: ATI International SRLInventor: James T. Battle