Abstract: A method, system and computer program product for automated technical support in a computer network having a client machine and at least one server. The method begins by selecting a diagnostic map useful in gathering diagnostic data for evaluating a given technical problem requiring diagnosis and correction. The diagnostic map encapsulates a set of one or more methods that, upon execution, explore the client machine and gather data. The diagnostic map is then executed by a diagnostic engine to generate a data set indicative of a current operating state of the client machine. This data set is forwarded from the client machine to the server for analysis. Based on the analysis performed at the server node, the data gathering process is repeated at the client machine, iteratively, until given information is available to a user of the client machine to correct the given technical problem.

Abstract: In a nonvolatile memory, select gates are self-aligned spacers formed on sidewalls of floating/control gate stacks. The same mask (1710) is used to remove the select gate layer from over the source lines (144), to etch trench insulation in the source line regions, and to dope the source lines. The memory can be formed in and over an isolated substrate region. The source lines can be doped at least partially before the trench insulation is etched, to prevent a short before the source lines and a region isolating the isolated substrate region from below. The memory can be erased by sectors, or alternatively a chip erase operation can be performed to erase all the cells in parallel. Peripheral transistor gates can be formed from the same layer as the select gates. The select gate spacers have extensions to which low resistance contacts can be made from overlying metal lines.

Abstract: A control circuitry for conveying video data in a flat panel display transmits video data using reduced swing differential signals that are time-multiplexed on a data bus. Data transmission schemes are provided to reduce data transitions on the data bus. A repeat last pixel scheme is used whenever the pixel data repeat horizontally on a display. A repeat last line pixel scheme is used whenever the pixel data repeat vertically on a display. A repeat last different pixel scheme is used whenever video data comprises mainly of monochrome information. In the alternate, a dynamic color pallet is used to store a few most frequently used pixel colors. When the current pixel color matches one of the colors stored, a pixel color address is transmitted instead of the pixel data itself. The use of reduced swing differential signaling on a time-multiplexed data bus together with one or more of the data transmission schemes achieves significant reduction in power consumption and electromagnetic interference generation.

Abstract: A computer system is provided that allows the content of a user's collection of fixed and removable media to be managed without regard to a specific type of media. The computer system performs equally well with files on floppy discs, removable hard-disks such as Iomega Zip, CDDA discs, CD-ROM discs, DVD-ROM discs and recordable or re-writeable variants of CD-ROMs and DVD-ROMs.

Abstract: A method and apparatus related to a data processing system contiguous-reference connection alignment mechanism. In one embodiment, an apparatus includes but is not limited to a data processing system contiguous-reference connection alignment mechanism, wherein the data processing system contiguous-reference connection alignment mechanism further includes but is not limited to a y-axis direction contiguous-reference alignment mechanism, wherein the y-axis direction contiguous-reference alignment mechanism further includes but is not limited to at least one fore-positioned data processing system connection guidance cylinder slot formed to catch a connection guidance cylinder misaligned in the y-axis direction and guide the connection guidance cylinder into substantial y-axis direction alignment. In one embodiment, a computer system includes but is not limited to a data processing system contiguous-reference alignment mechanism.

Abstract: A cathode structure suitable for a flat-panel display contains an emitter layer (213) divided into emitter lines, a plurality of electron emitters (229, 239, or 230) situated over the emitter lines, and a gate layer (215A) having an upper surface spaced largely above the electron emitters. The gate layer has a plurality of gate holes (215B) each corresponding to one of the electron emitters. The cathode structure further includes a carbon-containing layer (340, 240, or 241) coated over the electron emitters and directly on at least part of the upper surface of the gate layer such that at least part of the carbon-containing layer extending along and above the gate layer is exposed.

Abstract: A universal serial bus transceiver is disclosed. In one embodiment, the transceiver includes a differential transmitting amplifier with a first input terminal that receives a reference voltage, a second input terminal that receives a first data input signal at a level corresponding to the reference voltage, and a third input terminal that receives a second data input signal at the reference voltage level. The differential transmitting amplifier generates first and second bus data output signal at the bus signal level in response to the first and second data input signals. The transceiver also includes a first receiving amplifier with a first input terminal that receives the reference voltage and a second input terminal that receives a first bus data input signal at the bus signal level. The first receiving amplifier generates a first data output signal at the reference voltage level.

Abstract: An optical retro-reflective apparatus for application to reconfigurable displays for highway signs and other applications is disclosed. In a first preferred embodiment, the apparatus includes a retro-reflector such as a corner cube prism, three orthogonally arranged planer reflectors, or a plurality of either arranged as an array, or an array of micro-spheres or micro-prisms arranged as a corner-cube. In one embodiment, a holographic diffraction element is placed between a source of radiation such as visible light and one or more of the retro-reflectors. The diffraction element is made up of one or more stacked holographic devices in which pre-determined holographs are stored, operative to diffract a particular wavelength band of radiation (e.g. red, blue and green visible light). The hologram devices can be stacked and selectively deactivated so that the desired wavelength band (or color) to be diffracted is selected.

Abstract: A highly efficient bit encoder and a method related thereto are provided. The bit encoder transmit DC-balanced digital signals over a transmission line. To provide a DC-balanced signal, an input word's single-word disparity (SWD) value is compared to a running word disparity (RWD) value retrieved from a memory register. The RWD value indicates the cumulative DC-imbalance on the transmission line. If the disparity relationship of the SWD and the RWD satisfy a set of predefined rules, the input word is inverted to thereby offset the RWD. An inversion bit is appended to the digital input word to provide an output digital word to indicate to a receiver whether the transmitted output word is inverted to thereby permit recovery of the original system word. In one application, the DC-balanced signal transmits alternately control words and data words.

Abstract: A network controller, which allows data frames received to be held in an internal memory buffer, has the capability to selectively switch between a DMA mode of data transfer and a non-DMA mode of data transfer to move data frames from the internal memory buffer to a desired location. When the overflow of the memory buffer is anticipated, a DMA controller is automatically engaged to move the data frames to a system memory to prevent the received frames from being discarded. An auto-DMA decision logic engages the DMA controller based on factors such as the number of data frames accumulated in the memory buffer, remaining capacity of the memory buffer, frame loading and unloading rates, and time interval during which data frames have been received without completely unloading the memory buffer.

Abstract: A heat exchanger is used to transfer heat from water to liquid nitrogen. As heat is transferred from the water to the liquid nitrogen, the temperature of the water becomes lower and the liquid nitrogen converts to gaseous nitrogen. The cooled water and gaseous nitrogen are used by one or more semiconductor fabrication equipment in the semiconductor fabrication process. Thus, overall power consumption of the semiconductor fabrication process is lowered because water is cooled by passing the water by liquid nitrogen to convert the liquid nitrogen to gaseous nitrogen for use in the semiconductor fabrication process.

Abstract: A computation unit computes a division operation Y/X by determining the value of a divisor reciprocal 1/X and multiplying the reciprocal by a numerator Y. The reciprocal 1/X value is determined using a quadratic approximation having a form: Ax2+Bx+C, where coefficients A, B, and C are constants that are stored in a storage or memory such as a read-only memory (ROM). The bit length of the coefficients determines the error in a final result. Storage size is reduced through use of “least mean square error”techniques in the determination of the coefficients that are stored in the coefficient storage. During the generation of partial products x2, Ax2, and Bx, the process of rounding is eliminated, thereby reducing the computational logic to implement the division functionality.

Abstract: The present invention is directed to a multiport metering pump that can completely deliver a very small volume of liquid. The multiport metering pump includes a number of ports (or valve units), each of which can be used as either an outlet valve or an inlet valve. The multiport metering pump includes: a central gallery; a displacement unit; multiple valve units; and multiple conduits that respectively connect the displacement unit and the valve units to the central gallery. The displacement unit and the valve units communicate with the central gallery, and any of the valve units can be used as an inlet valve or outlet valve for the liquid delivery.

Abstract: A fan speed control system for controlling the operation and speed of a fan is described. The fan speed control system includes a power control block for supplying an output voltage to the fan. An integrated circuit fan controller causes a resistor divider circuit to operably divide a selected portion of the output voltage. The integrated circuit fan controller comprises a data register which receives values indicative of control or speed operands from a host. A logic state machine translates these values into appropriate logic signals and provides the signals to the resistor divider circuit. A timing reference or an oscillator controls the proper sequencing and timing relationship of the logic state machine. To turn the fan on, the following sequence of steps occurs. The power control block is turned off causing the output voltage not to be supplied to the fan. The logic state machine controls the resistor divider circuit to divide the output voltage to be supplied to the fan.

Abstract: A high voltage transistor exhibiting high gated diode breakdown voltage, low leakage and low body effect is formed while avoiding an excessive number of costly masking steps. Embodiments include providing a high gated diode breakdown voltage by masking the high voltage junctions from the conventional field implant and masking the source/drain regions from the conventional threshold adjust implant. Angled openings are formed in the field implant blocking mask so that the field implant at varying distances away from the junctions, thus achieving low leakage and a high gated diode breakdown voltage. The field implant blocking mask is extended over the channel area, thereby producing a transistor with low body effect.

Abstract: A triple-poly process forms a static random access memory (SRAM) which has a compact four-transistor SRAM cell layout. The cell layout divides structures among the three layers of polysilicon to reduce the area required for each cell. Additionally, a contact between a pull-up resistor formed in an upper polysilicon layer forms a “strapping” via which cross-couples a gate region and a drain region underlying the strapping via. Pull-up resistors extend across boundaries of cell areas to increase the length and resistance of the pull-up resistors.

Abstract: In a microprocessor system, a program counter circuit generates a program counter value that represents a retrieved instruction and that includes a more significant portion, a less significant portion, and a carry signal for use in determining a next program counter value. An execute program counter circuit generates an execute program counter value from the less significant program counter value and from the carry signal. The execute program counter value represents a program counter value of an executed instruction.

Abstract: An integrated circuit device having a first type of pads with a probing portion and a bonding portion. The integrated circuit device includes a memory cell array, a logic circuit, and a plurality of the first type of pads and a plurality of a second type of pads. The second type of pads are electrically connected to the logic circuit. The first type of pads are electrically connected to the memory cell array and the logic circuit. Only the probing portion of the first type of pads is contacted by probes during testing of the memory cell array, and the bonding portion is used exclusively for attachment of a bond wire to permit connection to an external system.

Abstract: A processor includes a “four-dimensional” register structure in which register file structures are replicated by N for vertical threading in combination with a three-dimensional storage circuit. The multi-dimensional storage is formed by constructing a storage, such as a register file or memory, as a plurality of two-dimensional storage planes.