Abstract: A marking system is provided for thin film magnetic disks in which the laser texturing stage in the manufacturing process for magnetic disks is used to form a single track marking zone. In this marking zone, information about the disk is serialized and stored in the form of long and short laser features, representing bits in a binary code. The length of the marking zone can be used to indicate additional information about the disk.

Abstract: A redundancy circuit of a semiconductor memory device includes a mode setting circuit that generates mode signal, an input selecting circuit that generates selecting signal in response to the mode signals, and a decoding circuit that, in response to the mode selecting signals, generates decoding signals. The redundancy mode signals include a bank redundancy mode signal, an array redundancy mode signal, and a column address group redundancy mode signal. The selecting signal identifies a bank in bank redundancy mode, an array in an array redundancy mode, and a column address group in column address group redundancy mode. The decoding signals initiate a replacement of a data I/O line pair associated to a defective memory cell in the semiconductor memory device. A redundancy method includes: generating the redundancy mode signals; generating the selecting signal in response to the redundancy mode signals; and generating the decoding signals.

Abstract: A system for dynamically determining and introducing time delay values for synchronizing different data signals. For transmitting the data signals, encoding time delay is measured in one encoder, a target encoder time delay value is determined, and the target encoder time delay value is utilized in another encoder to delay transmission of one data signal relative to the transmission of the other data signal. When encoded data signals are received and processed for presentation, the time required to decode a first data signal in a first decoder is measured, a target decoder time delay value is determined based on the time required to decode the first data signal, and the target decoder time delay value is utilized to delay presentation of a second data signal relative to the presentation of the first data signal.

Abstract: A receiver is provided which quickly and efficiently recognizes signals by including with the receiver a resolving circuit which is coupled to a signal generation circuit which provides a differential current. The resolving circuit is coupled to a latching circuit. The resolving circuit can operate with supply voltage levels as low as one threshold voltage. Also, the signal setup and hold times are inherently very small due to the high intrinsic bandwidth of the receiver. Other advantages include reduced power consumption, high speed operation, good rejection of input noise and power supply noise, ability to resolve small (e.g., 1.0 m Volt) voltage differences, reduced capacitive loading, and the ability to function with a variety of types of drivers, including HSTL, DTL and PECL.