Abstract: A digital data processing circuit comprising: a setting unit configured to set setting data on an audio signal processing circuit configured to generate an FM modulated signal based on the setting data, the FM modulated signal being a signal to be transmitted wirelessly to an FM radio receiver; and an output unit configured to output audio data for reproducing a predetermined audio signal while the setting unit sets the setting data on the audio signal processing circuit.

Abstract: A variable size first in first out (FIFO) memory is provided. The variable size FIFO memory may include head and tail FIFO memories operating at a very high data rate and an off chip buffer memory. The off chip buffer memory may be, for example, of a dynamic RAM type. The off chip buffer memory may temporarily store data packets when both head and tail FIFO memories are full. Data blocks of each of the memories may be the same size for efficient transfer of data. After a sudden data burst which causes memory overflow ceases, the head and tail FIFO memories return to their initial functions with the head FIFO memory directly receiving high speed data and transmitting it to various switching element and the tail FIFO memory storing temporary overflows of data from the head FIFO memory.