Abstract: Disclosed is a computer implemented method for determining a voltage reference error in a PCB design comprising receiving information about said PCB design, identifying a signal associated with said design, receiving one or more user defined voltage references for said signal, and comparing the user defined voltage reference to the voltages of the power planes adjacent to said signal.

Abstract: Disclosed is a method for synchronizing a bitstream, the method comprising comparing an incoming data byte of the bitstream with a predetermined byte pattern; writing a result of the comparison to a current write address in a FIFO; calculating a difference between a current read address in the FIFO and the current write address; asserting a synchronization signal when the difference equals a predetermined value; the result of the comparison is asserted; and an output of the FIFO at the current read address is asserted.

Abstract: Disclosed is a transport stream synchronizing system for synchronizing transport streams output from a plurality of transponders and decoded by a plurality of tuners. The transport stream synchronizing system comprises a tuner selector operable to select one transport stream out of a plurality of transport streams decoded by the plurality of tuners, a transport packet synchronizer operable receive the transport stream selected by the tuner selector, and synchronize the received transport stream; and a transport packet arbiter and router operable to receive a synchronized transport stream from the selected tuner, and route the received synchronized transport stream to a predetermined destination.

Abstract: A method is disclosed for electronically processing constraints rules defined in a previously developed first PCB design having a first constraints output file, to facilitate the development of a second PCB design having a second constraints output file. The second design has substantially identical topology to the first design and the second constraints output file comprises constraints for signals with identical attributes. The method includes several steps. Firstly, the board file of the first design is compared with the net list file of the second design to identify respective differences between the designs. On the basis of the established differences, a file attributes change report is generated. At least some data from the file attributes change report is stored into an attributes change file.

Abstract: A method for testing functionality of a chip checker is disclosed. The checker is arranged for generating a predetermined verification signal when the chip, upon receiving a predetermined input signal, generates a corresponding response signal. The method comprises the steps of developing a model of the chip, the model at least partially emulating at least one response of the chip by generating, upon receiving the predetermined input signal, the corresponding response signal. The method further supplies the developed chip model with the predetermined input signal. The checker is then used to test whether the generated response signal corresponds to the respective predetermined input signal. A failure of the checker to generate the predetermined verification signal indicates checker malfunction.