Abstract: According to a menu item selected in step S12 (a pressed command button), for a wafer exposing pattern, program goes to steps S13 and S14, and further, display in step S15, inspection in step S16 or modification in step 17 is performed; for a block pattern on a stencil mask, program goes to steps 13 and 24, and further display in step S25, inspection in step S26 or modification in step S27 is performed. In step S16 exposure simulation is performed, in step S15 a result thereof is displayed and in step S17 wafer exposing pattern data are modified based on the result. When a block pattern on a stencil mask is modified, the instances of the block pattern in the wafer exposing pattern data is simultaneously modified as well.

Abstract: The invention relates to cache apparatuses and a control method for managing cache memories in a multiprocessor system. A cache controller holds data which has to be invalidated for a cache coherence as data in a status where the validity is unknown, causes a cache hit in response to a reading request from a processor, provides the data as speculation data, and allows the processor to speculatively process the data. Therefore, since the data which has to be obtained from another cache or a main storage due to the invalidation is held in an Unknown status, a cache hit occurs. Thus, a data waiting time of the processor can be shortened.