Patents Represented by Attorney, Agent or Law Firm Stallna & Pollock LLP
  • Patent number: 6548839
    Abstract: An LDMOS array includes an array of alternating source regions and drain regions formed in a semiconductor substrate to define a checkerboard pattern of source and drain regions. A source contact is formed in electrical contact with each of the source regions in the array to connect the source regions in parallel. A drain contact is formed in electrical contact with each of the drain regions in the array to connect the drain regions in parallel. A drain ring is formed around the periphery of the checkerboard pattern and in electrical contact with the drain contact, providing redistribution of the current flow within the LDMOS array and thereby allowing safer hot carrier operation at higher biases than with the conventional layout.
    Type: Grant
    Filed: February 20, 2002
    Date of Patent: April 15, 2003
    Assignee: National Semiconductor Corporation
    Inventors: Andrew Strachan, Douglas Brisbin