Patents Represented by Attorney Stan Protigal
  • Patent number: 5443265
    Abstract: A golfing stroke trainer mat is provided with both back stroke and follow-through markings. Specifically, there are perpendicular and longitudinal lines running the length of the mat that aid in club head alignment and path. Measurement numbers to provide feedback on the length of both the back and follow through strokes. Uniquely, the invention can have colored matching sections to aid in the matching of the length of the strokes with or with out the numbering. The mat can be designed with colored lines, and/or lines having varying widths. Both of these schemes are designed to aid the golfer in controlling a pendulum stroke with equal back and follow through strokes. Another feature of the invention is that the golf clubs are marked with both a longitudinal and lateral line to match the lines on the golf mat. The mat is designed with a V shaped notch beginning at the center of the rectangular mat and extending to one of the longer ends.
    Type: Grant
    Filed: May 13, 1994
    Date of Patent: August 22, 1995
    Inventor: Charles H. Wheeler
  • Patent number: 5440240
    Abstract: A reusable burn-in/test fixture for discrete die consists of two halves. The first half of the test fixture contains cavity in which die is inserted. Electrical contact with bondpads or bumps on the die is established through a Z-axis anisotropic conductive interconnect material. When the two halves are assembled, electrical contact with the die is established. The fixture establishes the electrical contact and with a burn-in oven and with a discrete die tester. The test fixture need not be opened until the burn-in and electrical tests are completed. The fixture permits the die to be characterized prior to assembly, and the Z-axis anisotropic conductive interconnect material permits the die to then be transferred in an unpackaged form.
    Type: Grant
    Filed: November 5, 1991
    Date of Patent: August 8, 1995
    Assignee: Micron Technology, Inc.
    Inventors: Alan G. Wood, Warren M. Farnworth, David R. Hembree
  • Patent number: 5261776
    Abstract: The apparatus transfers a quantity of wafers from a first wafer boat to a second wafer boat. A wafer platform positioned beneath a wafer boat rises and transports the wafers to a pair of wafer grips which hold the wafers until the wafer platform is lowered and a second wafer about is in position to receive the wafers. The wafer platform is actuated by the negative pressure applied to alternating sides of a stage which divides a sealed cabinet into two portions. A vacuum is applied to alternating sides of the stage, while ambient air is introduced into the other side, causing the stage to move in the direction of lower pressure. The platform is affixed to the stage on at least two points.
    Type: Grant
    Filed: April 27, 1989
    Date of Patent: November 16, 1993
    Assignee: Micron Technology, Inc.
    Inventors: Ross H. Burck, Ernest E. Marks, Scott E. Moore
  • Patent number: 4962326
    Abstract: I/O lines on a CMOS circuit are precharged to preferred voltage levels in order to avoid latch up. The precharging is achieved by using N channel transistors to provide a precharge which is at a threshold voltage (V.sub.T) below bias voltage V.sub.CC, or (V.sub.CC -V.sub.T). This results in a lower forward bias when V.sub.CC bumps down after the I/O lines are floated. By lowering the precharge voltage by a level corresponding to a threshold voltage (V.sub.T), the allowed range of power supply voltage bumping is increased by this amount. This eliminmates the destructive effect of a negative bump of V.sub.BE, which would have presented a diode forward bias condition. Instead, the power supply may bump to (V.sub.BE +V.sub.T).
    Type: Grant
    Filed: July 22, 1988
    Date of Patent: October 9, 1990
    Assignee: Micron Technology, Inc.
    Inventors: Ward D. Parkinson, Wen-Foo Chern
  • Patent number: 4959325
    Abstract: The present invention constitutes an improvement of the Local Encroachment Reduction (LER) process developed by Tyler Lowrey at Micron Technology, Inc. of Boise, Idaho. LER consists of selectively etching a portion of the field oxide which has encroached into a DRAM cell's active area and then subjecting the cell to a high-energy boron implant to maintain adequate active area isolation. Although the boron implant effectively decreases the width of the depletion region between n+ active areas and p+ substrate, it has the undesirable effect of reducing the breakdown voltage at the n-p junctions in the bird's beak regions at the edges of the active regions, thus increasing the cell's susceptibility to gated-diode breakdown following creation of the cell plate. The present invention solves this problem by creating a graded junction in the bird's beak regions of the cell. The graded junction reduces the electric field intensity in the junction region, resulting in an increase in the breakdown voltage.
    Type: Grant
    Filed: February 24, 1989
    Date of Patent: September 25, 1990
    Assignee: Micron Technology, Inc.
    Inventors: Ruojia R. Lee, D. M. Durcan
  • Patent number: 4958088
    Abstract: A CMOS low power Schmitt type input buffer for a dynamic random access memory (DRAM) circuit. This buffer is further characterized in that a falling edge on the input has better than average noise immunity and has a slightly longer propagation time through the buffer than a rising edge.
    Type: Grant
    Filed: June 19, 1989
    Date of Patent: September 18, 1990
    Assignee: Micron Technology, Inc.
    Inventors: Mohammad H. Farah-Bakhsh, Stephen L. Casper
  • Patent number: 4957878
    Abstract: A dynamic randon access memory (DRAM) is formed in a series of masking steps, during which a first layer of polysilicon is anisotropically etched. After the anisotropic etch, junctions are added to the polysilicon through doping techniques. A second layer of polysilicon is then deposited and is isotropically etched. By the sequence, critical dimensions are established at preliminary mask layers and subsequent layers do not require the high degree of criticality of dimension.
    Type: Grant
    Filed: May 2, 1988
    Date of Patent: September 18, 1990
    Assignee: Micron Technology, Inc.
    Inventors: Tyler A. Lowrey, Randal W. Chance
  • Patent number: 4942576
    Abstract: Apparatus for comparing outputs of two digital devices and counting digital aberrations between them. One embodiment of this invention is the use of an XOR gate to compare the output of a DRAM under test to the output of a known good DRAM of corresponding operating characteristics, and the use of a counter to count the digital aberrations, known as badbits, between the two DRAMs.
    Type: Grant
    Filed: October 24, 1988
    Date of Patent: July 17, 1990
    Assignee: Micron Technology, Inc.
    Inventors: Jon P. Busack, Gary M. Johnson, Richard R. Clem
  • Patent number: 4939105
    Abstract: The present invention is a contact etch method which simultaneously smoothes a reflowed oxide profile so that separate phanarization photoresist coat and etch steps are unnecessary. This method is characterized in that it is fast, uses only one photoresist mask layer, etches contacts to poly and to substrate simultaneously, is done entirely with plasma etch technology in a single reactor, and builds up less polymer in the plasma reactor. The novel method eliminates a coat and an etch step, improving yield and reducing fabrication time. Lower polymer buildup means higher yields due to a cleaner process, and less downtime for reactor chamber cleaning.
    Type: Grant
    Filed: August 3, 1989
    Date of Patent: July 3, 1990
    Assignee: Micron Technology, Inc.
    Inventor: Rod C. Langley
  • Patent number: 4937465
    Abstract: One or more selected fuses among a plurality of fuses are blown by using electronic means to discharge a capacitor and route the resulting current spike to the selected fuse. Also, a driver output current is approximated by measuring suply currents for an unloaded output and for a loaded output and comparing the two supply currents. If the driver output is connected to the active end of a fuse, the supply current demanded by the driver indicates a state of the fuse. The invention finds particular utility when used on an integrated circuit memory array with fuse activated redundancy.
    Type: Grant
    Filed: December 8, 1988
    Date of Patent: June 26, 1990
    Assignee: Micron Technology, Inc.
    Inventors: Gary M. Johnson, Jon P. Busack
  • Patent number: 4926117
    Abstract: A two-piece burn-in board is used in semiconductor testing. The board can be disassembled so that it has ability to act as a device carrier wherein each individual device is completely isolated and as a standard burn-in board wherein all devices share the common signals. This ability to isolate or combine signals makes the board useable for functional device test/characterization and burn-in.
    Type: Grant
    Filed: May 2, 1988
    Date of Patent: May 15, 1990
    Assignee: Micron Technology, Inc.
    Inventor: Leland R. Nevill
  • Patent number: 4916570
    Abstract: A fluctuating voltage to be monitored is fed to the non-inverting input of a first op amp via a first input resistor; a reference voltage is fed to the inverting input of the second op amp via a second input resistor. The inverting input of the first op amp is taken from a first voltage divider connected between the reference voltage and ground; the non-inverting input of the second op amp is taken from a second voltage divider connected between the fluctuating voltage and ground. The power inputs of both op amps are connected to a positive voltage and ground. The output of both op amps is tied together, with a first feedback loop feeding the tied output voltage to the non-inverting input of the first op amp via a first high-resistance gain-setting resistor, and a second feedback loop feeding the tied output voltage to the inverting input of the second op amp via a second high-resistance gain-setting resistor.
    Type: Grant
    Filed: May 11, 1989
    Date of Patent: April 10, 1990
    Assignee: Micron Technology, Inc.
    Inventor: James L. Dale
  • Patent number: 4915597
    Abstract: Valve and channeling improvements in a filter pump head assembly used for dispensing photoresist in a semiconductor manufacturing facility.
    Type: Grant
    Filed: December 19, 1988
    Date of Patent: April 10, 1990
    Assignee: Micron Technology, Inc.
    Inventor: Scott E. Moore
  • Patent number: 4914269
    Abstract: A method of sealing a ceramic lid on a ceramic semiconductor package with a high-power laser beam. As an aid to package assembly prior to the fusion of the package lid to the package body, a lid recess is created around the die installation cavity of the package body. Following the installation of a die within a package cavity, the package body is retrieved from a process tray by a pick and place robot and placed in a position locating fixture. The same robot then retrieves a ceramic lid from an automatic lid dispensing unit, and places it within the lid recess of the package body. With the lid positioned within the recess, a Yttrium-Aluminum-Garnet (YAG) laser with beam splitter optics is moved by an X-Y table arm precisely over the top of the package. Moving with a linear speed of approximately 2.1 cm/sec. and with a power setting of approximately 170 watts, the split beam YAG laser simultaneously fuses a pair of opposite edges of the lid to the adjacent edges of the recess.
    Type: Grant
    Filed: July 24, 1989
    Date of Patent: April 3, 1990
    Assignee: Micron Technology, Inc.
    Inventors: Larry D. Kinsman, Steven H. Laney, Wade D. Jorgensen
  • Patent number: 4910866
    Abstract: A method of manufacturing a series of leadframe strip carriers, the individual members of the series having common external dimensions to facilitate production handling equipment setup and internal slot dimensions which vary to accommodate the various widths of available leadframe strips. This new method of manufacturing leadframe strip carriers results in a much lower unit cost, as compared to carriers manufactured from aluminum extrusions. This has been achieved using an injection molding process employing a single mold which produces constant length, width and height dimensions throughout the series, and which has an internal form die, the position of which can be varied with spacing inserts that can be either removed or transferred to the other side of the mold cavity as the mold is modified for progressively-narrower leadframe strips. To ensure durability, highly-abrasion resistant, fiber-reinforced plastic material is used to create the carriers.
    Type: Grant
    Filed: February 21, 1989
    Date of Patent: March 27, 1990
    Assignee: Micron Technology, Inc.
    Inventor: Timothy J. Allen
  • Patent number: 4906314
    Abstract: A process for simultaneously applying precut protective swatches of precured polymer film to each semiconductor die on a wafer, whereby an indexed greater-than wafer-width strip of precured polyimide film having a heat-attach adhesive on its lower surface is die punched to remove essentially half of the scrap film, material between each of the individual portions on the film which dimensionally correspond to the areas of individual dies on a silicon wafer requiring protection. Each punched area corresponds to areas on the wafer die matrix that are to remain unprotected. Following this first punching, a strip of dimensionally-stable backing paper coated with heat-release adhesive is bonded to the upper surface of the polyimide strip in the region which will become matrices of swatches. The double layer strip is then subjected to second die-punch process which removes the remaining scrap film material between the individual swatches.
    Type: Grant
    Filed: December 30, 1988
    Date of Patent: March 6, 1990
    Assignee: Micron Technology, Inc.
    Inventors: Warren M. Farnworth, Alan G. Wood
  • Patent number: 4897568
    Abstract: A pumpdown circuit uses voltage sensing to bring a low node to a potential of V.sub.SS +V.sub.T by first grounding the node and then floating the node to the V.sub.SS +V.sub.T potential. When a sensing node is at the V.sub.SS +V.sub.T potential, the sensing node is maintained at a level above ground by leakage current through a pump-up circuit. Biasing the digit and digit* lines to a potential V.sub.T above ground reduces current (amperage) requirement, because the digit and digit* lines do not have to be discharged completely to ground. The momentary discharge of the sense amp node to ground allows the sense amp to behave like a conventional sense amp during initial sensing, thereby allowing a minimum digit/digit* sensing potential to approximate ground plus V.sub.T.
    Type: Grant
    Filed: September 30, 1988
    Date of Patent: January 30, 1990
    Assignee: Micron Technology, Inc.
    Inventors: Wen-Foo Chern, Ward D. Parkinson, Zhitong Chen, Gary M. Johnson, Tyler A. Lowrey, Thomas M. Trent
  • Patent number: 4892122
    Abstract: Apparatus generally for bending wire and particularly for bending and aligning probe pins. The preferred embodiments consists of a small diameter stiff wire with one end formed into a small closed loop, and the other end attached to a handle.
    Type: Grant
    Filed: December 19, 1988
    Date of Patent: January 9, 1990
    Assignee: Micron Technology Inc.
    Inventor: John M. Ickes
  • Patent number: 4891794
    Abstract: A three port memory device has two serial ports and a random access memory port. The random access memory port is addressed to a random access memory in a conventional manner, using RAS and CAS address signals. Data may also be supplied and retrieved through two serial ports to a pair of serial access memories for transfer between the serial ports and the random access memory. This configuration permits formatted data to be simultaneously assessed through the two serial ports, while the random access memory port is being accessed.
    Type: Grant
    Filed: June 20, 1988
    Date of Patent: January 2, 1990
    Assignee: Micron Technology, Inc.
    Inventors: Glen E. Hush, Jeffrey S. Mailloux, Eugene H. Cloud
  • Patent number: 4885841
    Abstract: During solder-reflow attachment of surface-mount electronic components to a printed circuit board, vibrational energy sufficient to overcome the static coefficient of friction between the leads of a component and their respective connector pads is applied to the board, with the result that the surface tension of the molten solder between the leads and the pads will produce a best-fit alignment of the leads of each component on their corresponding connector pads.
    Type: Grant
    Filed: February 21, 1989
    Date of Patent: December 12, 1989
    Assignee: Micron Technology, Inc.
    Inventor: John P. McNabb