Abstract: A dynamic pipeline for a processor, including multiple latch stages for providing data to corresponding operation elements and multiplexers with associated control logic for bypassing one or more latch stages and operation elements to execute simpler instructions. For a graphics processor, multiplexers select input pixel values and alpha blending values from either internal or external sources. The pixel values are processed through an arithmetic and logic unit for performing logic operations with other pixel values or with offset scaler values. The alpha values are inverted for performing alpha blending functions. The pixel and alpha values are then provided to a first set of latches for providing latched data to the inputs of a multiplier. The output of the multiplier and another offset scalar value are provided to a second set of latches for providing latched data to an arithmetic element.

Abstract: A method and apparatus for sharing objects among a group of processes may be accomplished by using a causal time stamp for each conveyance of information between the members of the group of processes. When a process receives an object request from another process, wherein the object request includes identity of the process requesting the objects, a request causal time stamp, and the objects being requested, the receiving process updates its current causal time stamp and grant causal list. The grant causal list includes a prioritized listing of outstanding object requests, where prioritization is based on a predetermined total ordering procedure. Once the grant causal list has been updated, the receiving process determines whether it has one of the needed objects being requested and the request is of a higher priority. If so, the receiving process generates a grant message for the requesting process.

Abstract: The present invention discloses an electroluminescent panel and a power supply circuit for applying voltages of alternating current to the electroluminescent panel. The power supply circuit is comprised of a voltage converter, an electric power source, a charge controller for controlling the transfer of energy from the power source to the electroluminescent panel, and a discharge controller for controlling the transfer of energy from the electroluminescent panel to the power source.

Abstract: A computer system for communicating with a network including a host processor, memory, an interface bus and a network interface device for reducing data transfer latency between the computer system and the network. The network interface device includes a buffer for temporarily storing data, a media interface device for transferring data between the buffer and the network, a bus interface for transferring data between the computer system's memory and the buffer, and a local processor for writing a unique value at a predetermined location within the buffer, for periodically comparing the data value at the predetermined location with the unique value and for initiating data transfer from the buffer to the computer's memory when the data value does not match the unique value. The network interface device is preferably a network interface card (NIC) for plugging into a slot of the interface or expansion bus of the computer system.

Abstract: A hash system for selecting a destination network port for each of a plurality of binary address values, such as media access control (MAC) addresses, received by a plurality of network ports including a hash memory for receiving binary hash values and for providing a corresponding port number identifying a destination network port. Each of the network ports includes hash logic for receiving a binary address value, for selecting a subset of bits of each received binary address value as a binary hash value, for providing the binary hash value to the hash memory and for receiving a corresponding port number. The subset of bits are determined by a bit enable value.

Abstract: A communication protocol detection system for enabling a network system to detect and interface one or more network devices each operating according to at least one of a plurality of different communication protocols. In one embodiment, a network interface card (NIC) is capable of operating according to one of two different communication protocols, such as the 10Base-T and 100Base-TX Ethernet Standards. The NIC includes two corresponding transceivers, where the transceivers are interfaced to a network connector for interfacing an external network device. Control logic initially enables the 10Base-T transceiver to determine if link pulses are detected. If link pulses are detected, the 100Base-T transceiver is enabled to determine if it detects the link pulses. If so, the 100Base-T transceiver is used to establish communications, and if not, the 10Base-T transceiver is used.

Abstract: A termination scheme for twisted-wire pairs for network communication systems, such as Fast Ethernet 100BaseTX, where the wires are electrically connected together and a single resistor is coupled in series between the junction of the wires and ground. A capacitor may also be coupled between the resistor and ground for DC isolation purposes. The single resistor preferably has a resistance equivalent to half of the common mode impedance between the unused pairs. The two wires of each pair are shorted together since there is no differential signal between the two wires. In this manner, two differential impedance resistors are eliminated, thereby reducing size and cost of the system without degrading performance.

Abstract: A communication system for allowing a master to send commands to one or more slave devices across a normally static digital signal line of a bus. The master includes command logic for asserting a sequence of digital pulses according to a predetermined protocol with inherent timing to clock each data bit into a slave device. The master transmits several data bits to form each command, where each data bit is combined with clocking pulses to implement the self-clocking scheme. In particular, an initial data pulse incorporates a data bit to initiate a data phase. Each slave device includes a state machine which detects the data pulse and enables a sample and hold or latch circuit to capture the data bit. Then a clock pulse followed by a reset pulse is sent to clock the data into the slave device and reset the state machine. The slave also includes shift register logic to hold a command bit and address bits for each command.

Abstract: A fan speed monitoring system for interfacing a fan, including a fan drive and sensing circuit for maintaining the voltage of the fan's TFSC pin above a minimum voltage level, thus maintaining continuous power to the fan. The fan drive and sensing circuit includes a control loop having an isolation resistor for enabling superposition of fan pulses asserted by the fan on the TFSC pin. The fan speed monitoring system also includes a filter circuit for filtering and amplifying the fan pulses and providing corresponding filtered pulse signals. The fan drive and sensing circuit includes an active control loop for maintaining the voltage of the TFSC pin at an average level above the minimum voltage level, while also enabling inclusion of the fan pulses. The filter circuit preferably includes an AC amplifier for amplifying the fan pulses and a level transition comparator for converting the amplified fan pulses to the filtered pulse signals having the desired form.

Abstract: Interpolation method and apparatus for rendering polygons into a pixel grid. A software driver receives vertices of each polygon and identifies a main slope traversing the vertical extent of the polygon, where the other sides are opposite slopes. The software driver determines initial and incremental width values for width interpolation, rather than edge walking the opposite slopes. The interpolator logic includes a width counter for loading the width value, so that each orthogonal scan line is complete when the width counter reaches terminal count rather than comparing each pixel with the opposite slope. An interpolation procedure thus allows randomly-oriented triangles and other polygons having a main slope, up to two opposite slopes and up to three orthogonal sides to be drawn in a single command.

Abstract: A feedback sensing system including a control circuit for detecting power failure of either power supply, and for controlling first and second switch circuits to modify the feedback sensing path of the other supply to the output load. In this manner, when one power supply fails, the feedback sensing path of the other power supply is rerouted to the output node to directly monitor and regulate the voltage across the load. Each switch circuit preferably operates to switch between two nodes along the respective output paths of the power supply, including a first node located before the current control device and a second node located between the current control device and the load. In one embodiment, each switch circuit includes two switches operated in a mutually-exclusive manner.

Abstract: A power loss detection system for a power supply including a main converter for providing regulated power, an activation circuit for mining on and off the main converter based on an active low activation signal, a standby power circuit for providing a standby power signal, and an internal pullup resistor coupled between the standby power and activation signals. The power supply asserts a power status signal indicative of the status of regulated power. Alternatively, an external detection circuit monitors the regulated power from the power supply and asserts a power loss signal indicative thereof. The control circuit asserts the activation signal low to turn on the main converter or floats the activation signal to turn off the main converter. If the power good or power loss signal indicates loss of regulated power, the control circuit floats the activation signal. If the activation signal goes or remains low after the activation signal is floated, then the power source has failed.

Abstract: A stage assembly for a substrate processing system including a cassette support assembly for receiving and supporting a cassette and an actuation and support assembly for supporting and moving the cassette and cassette support assembly between a loading position and a processing position. The processing position provides convenient and efficient access by a central processing system, and the loading position preferably places each cassette closer to, and aligned with, a front panel of the processing system for convenient access by an operator. The actuator and support assembly preferably includes a frame assembly and a rotating plate pivotally mounted to the frame assembly, where the cassette support assembly is mounted to the rotating plate for pivoting relative to the frame assembly. An actuator assembly mounted to the frame assembly flits the cassette support assembly between the loading and processing positions. A shaft assembly pivotally mounts the cassette support assembly to the rotating plate.

Abstract: A processor having two separate and relatively independent memory controllers to achieve a dual interface architecture. A first memory controller is coupled to the host interface for retrieving data and instructions and a second memory controller is coupled to an independent local bus for interfacing with a frame buffer memory. A depth buffer may also be coupled to the local bus if desired. Address multiplexor logic is preferably included to allow either memory controller to address either external bus. Multiplexor and buffer logic is also preferably included to allow data transfer in either direction. Preferably, the processor is a graphics processor and both memory controllers are programmable for different addressing formats, such as linear and X/Y in the preferred embodiment. In this manner, data is transferred from host to local memories, and vice versa, in any desired format without delays due to memory controller reconfiguration.

Abstract: A universal offline switch mode power supply including an input stage having an input filter inductor and a switch for switching between a first lower AC input voltage or a second higher AC input voltage. A bridge rectifier full-wave rectifies the higher AC voltage when the switch is in a first position, where the filter inductor serves to filter the higher AC voltage. The higher AC voltage is preferably approximately 230 V rms. The bridge rectifier and two bulk capacitors serve to double the lower AC voltage when the switch is in a second position, where the lower AC voltage is preferably approximately 115 V rms. Also, the input filter is bypassed for the lower AC voltage. The switch is preferably an SPST switch. In the preferred embodiment, the inductor is placed between one AC input line and one input of a bridge rectifier circuit. The outputs of the bridge rectifier circuit are placed across two series input bulk capacitors and to the input of a switchmode power converter.

Abstract: A power supply system including a power supply providing power to an electronic device through current share circuitry, which includes a second connector for receiving power from an external power supply. The power supply is preferably a fault-tolerant power supply so that the electronic device receives continuous power in the event of partial failure. When the fault-tolerant power supply partially fails, the external power supply is connected to the second connector of the current share circuitry, which is switched to temporarily provide power to the electronic device from the external power supply. The power supply is then replaced while the external power supply provides power, so that power to the electronic device is continuously maintained. The electronic device thus experiences zero down-time. Even in low-end systems with a single power supply, down-time is substantially reduced. The external power supply is connected internally or through an external connector on the electronic device.

Abstract: An incremental orthogonal error correction process for 3D graphics for correcting errors or otherwise reducing abrupt changes in the characteristics of adjacent pixels while interpolating a polygon into a pixel grid. Error values are calculated for each desired characteristic to be corrected, where the error values are calculated based on the slope of the main slope and the orthogonal slope of the corresponding characteristic value. Thus, the error values adjust the characteristics of the pixels in the scan line to adjust for the slant of the main slope of the polygon. An interpolator for each corrected characteristic accumulates the error value in the opposite direction as the corresponding orthogonal slope. When the fractional component of the x parameter overflows, the orthogonal slope values are subtracted from the corresponding accumulated error values to thereby reduce the magnitude of the error values.

Abstract: A fault tolerant isolation system providing fault tolerant electrical isolation between different components receiving power from separate power sources regardless of which of the power sources fails. One power source provides operating voltage to an isolation device, which is a transceiver, buffer, quick switch, etc. The other power source activates a transistor switch coupled to the output enable input of the isolation device, and a current limit device is provided between the output enable and power inputs of the isolation device. In this manner, failure of either power source disables the isolation device and therefore provides fault tolerant isolation between the devices on either side. In the preferred embodiment, the isolation device acts as a high impedance open switch if its power is removed thereby isolating the devices on either side.

Abstract: A fail-safe system for monitoring the voltage of a backup battery of a portable computer system to prevent excessive drainage of the backup battery. The backup battery is primarily provided to maintain voltage to the configuration memory of the portable computer during swapping of the main battery. A timing circuit allows the backup battery to provide power to other, low power system components for a limited time, such as two minutes, while the main battery is being replaced. In the fail-safe circuit, a comparator circuit monitors the voltage of the backup battery and asserts a signal in the event its voltage falls to a predetermined minimum level. A switch circuit correspondingly disconnects the backup battery from the other system components, thereby conserving the energy of the backup battery.

Abstract: A presumptive mode computer aided design and drafting system for interactively manipulating and displaying graphic objects that employ predefined rules to govern the geometric layout and logical relationships representing a physical design, schematic or process flow diagram. The system is configured to comply with the rules employed by various design disciplines. Specific interactive computer graphics behavior is dynamically accessed to interactively update graphic object relationships according to rules of geometric conduct. The rules of geometric conduct may be stored in external databases along with parameters to verify the logical relationships of the graphic objects used in the drawing. Object orientation is employed in the software design of the system to allow new devices or procedures to adopt the behavior of existing definitions. In the preferred embodiment, a selected object floats with a cursor in a graphic environment until located in proximity with underlying graphic objects.