Abstract: An integrated circuit has primary devices and redundant devices being selective substituted for the primary devices through at least one fuse. The fuse includes a first layer having at least one fuse link region, a second layer over the first layer and cavities in the second layer above the fuse link region.
Type:
Grant
Filed:
May 21, 2001
Date of Patent:
May 20, 2003
Assignee:
Infineon Technologies AG
Inventors:
Axel C. Brintzinger, Edward W. Kiewra, Chandrasekhar Narayan, Carl J. Radens