Abstract: The present invention is directed to an integrated circuit device having at least one memory section including a plurality of memory cells. The device includes an internal register to store an identification value which identifies the device on a bus. The device further includes interface circuitry, coupled to the bus, to receive identification information and a read request. The interface circuitry includes a plurality of output drivers and comparison circuitry. The output drivers are coupled to the bus to output data on the bus in response to the read request. The data is output synchronously with respect to first and second external clock signals when the comparison circuitry determines the identification information corresponds to the identification value.

Abstract: The present invention includes a memory subsystem comprising at least two semiconductor devices, including at least one memory device, connected to a bus, where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices, where the control information includes device-select information and the bus has substantially fewer bus lines than the number of bits in a single address, and the bus carries device-select information without the need for separate device-select lines connected directly to individual devices.The present invention also includes a protocol for master and slave devices to communicate on the bus and for registers in each device to differentiate each device and allow bus requests to be directed to a single or to all devices. The present invention includes modifications to prior-art devices to allow them to implement the new features of this invention.

Abstract: A method and apparatus for assigning identification values to memories. A master resets identifiers of a first memory and a second memory by sending a reset signal on a line that is coupled in a daisy-chained manner to the first and second memories and also coupled to the master. The master places a first identification value on a data bus coupled to the master and to the first and second memories. The first memory stores the first identification value on the data bus as an identifier for the first memory when the master sends a first storage signal to the first memory via the daisy-chained line. The master places a second identification value on the data bus. The second memory stores the second identification value on the data bus as an identifier for the second memory when the master sends a second storage signal to the second memory via the daisy-chained line.