Abstract: An improved and new method for forming a planarized integrated cirsuit structure has been developed. The method uses a combination of etchback and chemical/mechanical polishing (CMP), in which the etchback process uses a tailored mask to compensate for non-unifomity of material removal by the subsequent chemical/mechanical (CMP) process, thereby resulting in improved planarization and superior thickness uniformity.

Abstract: A method of creating a non-volatile memory device, featuring self-alignment of a control gate structure, to an underlying floating gate structure, has been developed. The formation of a first polysilicon floating gate shape, completely covering the semiconductor substrate, with openings only to underlying field oxide regions, prevents a deleterious trenching phenomena from occurring during a subsequent patterning, used to define an overlying, control gate structure. A photoresist shape is used as a mask to allow patterning of the control gate structure to be performed, via an anisotropic procedure, applied to a polysilicon layer, followed by the continuation of the anisotropic RIE procedure, applied to the first polysilicon floating gate shape, creating the floating gate structure.