Abstract: A method for forming and using silicide test structures to monitor and evaluate the quality of a semiconductive junction after the formation of a silicide layer over the junction is described. Two specially designed test structures are formed for in-line testing in the kerf of an integrated circuit wafer. The test structures comprise a silicide region formed over a diffusion region which is formed concurrently with diffusion and silicide regions which form contacts of the integrated circuit dice. The test structures are fitted with probe pads connected to semiconductive element of the junction region. A first structure is designed to measure bulk junction leakages, has the silicide contact layer spaced away from the junction edge. A second structure, designed to measure edge related junction leakage phenomena, has a serpentine edge to which the silicide layer extends and a plurality of interior openings which serve as EMMI windows.

Abstract: A method for forming within an integrated circuit a high areal capacitance planar capacitor, and the high areal capacitance planar capacitor which results from the method. There is first formed upon a semiconductor substrate a first planar capacitor electrode. The first planar capacitor electrode has a first planar capacitor dielectric layer formed thereupon, and the first planar capacitor dielectric layer has a second planar capacitor electrode formed thereupon. Formed then upon the semiconductor substrate is a Pre-Metal Dielectric (PMD) layer which is planarized until the surface of the second planar capacitor electrode is fully exposed. There is formed upon the second planar capacitor electrode a second planar capacitor dielectric layer. Finally, there is formed upon the second planar capacitor dielectric layer a third planar capacitor electrode.

Abstract: A new probe socket is provided that allows for high speed and dependable contacting of points of contact on the Device Under Test. The new probe socket is aimed at a testing environment where semiconductor devices are mounted on device or package strips.

Abstract: A number of air actuated valves are added to a conventional apparatus for treating semiconductor wafers with HMDS, hexamethyl-disilazane, vapor to improve the adhesion between the wafers and resist layers. These valves allow for automatic purging of the HMDS vapor from the pipes in the apparatus by dry nitrogen thereby preventing HMDS vapor condensation in the pipes which leads to contamination of the HMDS supply. The valve system prevents any backstreaming of nitrogen gas into the HMDS supply tank.

Abstract: A method of forming a silicon oxide isolation region on the surface of a silicon wafer consisting of a thin layer of silicon oxide on the wafer, a layer of impurity-doped polysilicon, and a layer of silicon nitride. The oxidation mask is formed by patterning the silicon nitride layer and at least a portion of the doped polysilicon layer. The silicon oxide field isolation region is formed by subjecting the structure to a thermal oxidation ambient. The oxidation mask is removed in one continuous etching step using a single etchant, such as phosphoric acid which etches the silicon nitride and polysilicon layers at substantially the same rate to complete the formation of the isolation region without pitting the monocrystalline substrate.

Abstract: A cost-effective and manufacturable method for producing ROM integrated circuits with closely-spaced self-aligned conductive lines, on the order of 0.3 micrometers apart, is described. Parallel, conductive semiconductor device structures are formed in a semiconductor substrate. An insulating layer is formed over the semiconductor substrate. A first conductive polysilicon layer is formed over the insulating layer. The first conductive polysilicon layer is patterned to form first polysilicon conductor lines which are parallel to each other, and orthogonal to the parallel, conductive semiconductor device structures. A first silicon oxide layer is formed on and between the first polysilicon conductor lines. The first silicon oxide layer is anisotropically etched to produce sidewall structures on the first polysilicon conductor lines. A second silicon oxide layer is formed on and between the first polysilicon conductor lines.