Abstract: A new design for a high voltage bipolar transistor is disclosed. Instead of a buried subcollector (which would be N+ in an NPN device), a buried P+ layer is used. The presence of this P+ layer results in pinch-off between itself and the bipolar base. This allows much higher breakdown voltages to be achieved. In particular, the device will not break down at the bottom of the base-collector junction which is the weak spot for conventional devices. A process for manufacturing this device is described. A particular feature of this new process is that the N type epitaxial layer that is grown over the P+ layer is only about half the thickness of its counterpart in the conventional device. The process is fully compatible with conventional BiCMOS processes and has lower cost.

Abstract: A dynamic mask exposure system and method includes a support for a workpiece, a source of a beam of exposure radiation, and a transmissive dynamic phase-shifting mask with orthogonally arranged matrices of actuator lines and binary pixel units which are opaque or transparent as a function of control inputs to the actuator lines. The transmissive dynamic mask has a top surface and a bottom surface. A control system is connected to supply pixel control signals to the actuator lines of the transmissive dynamic mask to form a pattern of transparent regions and opaque regions. The beam is directed down onto the top surface of the mask. A workpiece and/or an image detection element for detecting a pattern of radiation projected thereon is located on the top surface of the support. The beam passes through the transparent regions and projects a pattern from the mask onto the support where the workpiece or onto the image detection element is to be located.

Abstract: A method for removing a photoresist layer from a semiconductor substrate following a conventional dry etching step. A first wet chemical treatment strips the photoresist. A second dry ash with oxygen plasma completes the photoresist removal. To assure complete removal of photoresist imbedded on or within the material underlying the photoresist film, the semiconductor substrate is preheat treated to a temperature in the range of 150 to 250 degrees Centigrade to release the photoresist prior to the second dry ash with oxygen plasma operation. In particular, this method eliminates photoresist extrusion defects from occurring during a bond pad alloy operation.

Abstract: An ESD protection circuit is connected to an integrated circuit to dissipate an electrostatic charge from an ESD source placed in contact with two terminals of the integrated circuit to prevent damage to the integrated circuits. The ESD protection circuit has a ESD shunting circuit for shunting the electrostatic charge from integrated circuit. The ESD shunting circuit has a first port connected to one terminal of the integrated circuit, a second port connected to another terminal of the integrated circuit, and a third port. The ESD protection circuit additionally has an ESD detection circuit. The ESD detection circuit has a first input port connected to the one terminal of the integrated circuit, a second input port connected to the other terminal of the integrated circuit, and an output port connected to the third port of the ESD shunting circuit.

Abstract: Within a method for forming a microelectronic fabrication, there is first provided a substrate. There is then formed over the substrate a blanket aluminum containing conductor layer. There is then formed over the blanket aluminum containing conductor layer a masking layer. There is then etched, while employing a plasma etch method, the blanket aluminum containing conductor layer to form a patterned aluminum containing conductor layer while employing the masking layer as an etch mask layer, where the plasma etch method employs an etchant gas composition comprising at least one fluorine containing etchant gas and at least one halogen containing etchant gas other than a fluorine containing etchant gas. There is then formed contacting the patterned aluminum containing conductor layer a conformal dielectric liner layer. There is then formed upon the conformal dielectric liner layer a spin-on-glass (SOG) planarizing layer.

Abstract: A method for developing a semiconductor device low resistance electrical contact is described. In this process a gate oxide layer followed by a polysilicon layer is deposited on the semiconductor substrate in proximity to the device contact area. It is subsequently patterned with photoresist and etched to produce the desired gate structure. This is followed by a deposited layer of silicon dioxide or silicon nitride (SIN) which is appropriately patterned and etched to form gate isolation spacers. Then a nominal 300 Å layer of silicon nitride (SIN) is deposited followed by a layer of tetraethyl orthosilicate (TEOS) or borophosphosilicate glass (BPSG). The contact area is defined by photolithography, and the passivation layers are etched either by a dry etch such as a RIE process, or a combination of a wet BOE process followed by a dry etch, to form the metal contact holes.

Abstract: The present invention provides a method of fabricating a vertical hard mask/conductive pattern profile. The process begins by forming a polysilicon or more preferably a polysilicon and silicide conductive layer over a semiconductor substrate. A silicon oxynitride hard mask layer is formed over the conductive layer. The silicon oxynitride hard mask layer is patterned to form a hard mask pattern. The conductive layer is patterned to form a conductive pattern using Cl2/He—O2/N2 etch chemistry, thereby forming a hard mask/conductive pattern profile that is vertical.

Abstract: A non-magnetic conductor material, a magnetic transducer element having formed therein a non-magnetic conductor layer formed of the non-magnetic conductor material and a method for forming a magnetic transducer element having formed therein the non-magnetic conductor layer formed of the non-magnetic conductor material. The non-magnetic conductor material comprises an alloy comprising nickel and at least one non-magnetic conductor metal selected from the group consisting of copper at a weight percent of from about 45 to about 90, zinc at a weight percent of from about 20 to about 75, cadmium at a weight percent of from about 35 to about 85, platinum at a weight percent of from about 55 to about 90 and palladium at a weight percent of from about 75 to about 95. The non-magnetic conductor material contemplates the magnetic transducer element and the method for forming the magnetic transducer element.