Patents Represented by Attorney Stephen B. Ackermann
  • Patent number: 5897364
    Abstract: A method for forming N- and P-channel transistors having shallow junctions in an integrated circuit device is described. A semiconductor substrate is provided having active regions separated from one another by isolation regions wherein there is a N-channel active region and a P-channel active region and wherein gate electrodes and associated lightly doped source and drain regions have been formed in each of the active regions. A layer of borosilicate glass is deposited overlying the semiconductor substrate. A photoresist mask is formed over the P-channel active region. The borosilicate glass layer is etched away where it is not covered by the photoresist mask thereby leaving the borosilicate glass layer only overlying the P-channel region. The photoresist mask is removed. A layer of phosphosilicate glass is deposited overlying the semiconductor substrate.
    Type: Grant
    Filed: June 24, 1996
    Date of Patent: April 27, 1999
    Assignee: Chartered Semiconductor Manufacturing, Ltd.
    Inventor: Yang Pan