Abstract: A communication system includes a receiver for receiving a serial bit stream from at least one communication channel, and a decoder, in communication with the receiver, for decoding words from the received serial bit stream, the words being defined at least in part by word boundaries in the received serial bit stream. The decoder contemporaneously synchronizes detection of bits and detection of the word boundaries in the received serial bit stream. The decoder preferably decodes digitized video signal information in the serial bit stream according to a Transition Minimized Differential Signalling protocol. The receiver and decoder are preferably part of an integrated circuit chip.

Abstract: A modulo mi adder and a modulo mi,j scaling unit for use with an RNS. The adder includes a modulo mi barrel shifter, and a dynamic storage unit coupled to the barrel shifter to store the output of the barrel shifter. In a preferred embodiment, the dynamic storage unit includes one dynamic latch for each output line of the barrel shifter, with each of the dynamic latches including a clocked inverter in cascade with an inverter. One modulo mi,j scaling unit includes a modified modulo mi barrel shifter that performs both residue conversion and an arithmetic operation. The residue conversion is performed without using combinational logic. In one preferred embodiment, the modified barrel shifter performs the residue conversion though mi–mj additional columns that replicate normal columns for all modulo mi input lines that are congruent modulo mj.

Abstract: A flexible Galois Field multiplier is provided which implements multiplication of two elements within a finite field defined by a degree and generator polynomial. One preferred embodiment provides a method for multiplying two elements of a finite field. According to the method, two input operands are mapped into a composite finite field, an initial KOA processing is performed upon the two operands in order to prepare the two operands for a multiplication in the ground field, the multiplication in the ground field is performed through the use of a triangular basis multiplier, and final KOA3 processing and optional modulo reduction processing is performed to produce the result. This design allows rapid redefinition of the degree and generator polynomial used for the ground field and the extension field.

Abstract: Enhanced resolution video sequence results from construction of enhanced resolution key frames and synthesis of enhanced resolution non-key frames. Key frames are constructed by processing a plurality of initial resolution frames in order to produce the enhanced resolution image components of the key frame. Non-key frames are synthesized using the enhanced resolution image component of the key frames and image component motion determinations from initial resolution frames using an image warping technique. Non-key frame image components are further improved by blending and error correction processes.

Abstract: A method and apparatus for buffering 2-dimensional graphical image data to be supplied to a scrolling display controller. A 2-dimensional, circularly addressed linear data buffer is used to store a portion of an entire image. The data buffer is larger than the amount of data displayed at one time. A user enters scrolling commands and the display scrolls around the data initially in the buffer. New data is loaded into the buffer as the displayed data approaches the edge of the buffered data.

Abstract: A method for storing a plurality of still images to form a panoramic image. The method comprising the steps of receiving a first image forming a part of a series of images to form a panoramic image and storing the first image in memory. When one or more subsequent images after the first image are received the steps of calculating one or more panoramic parameters between a current image and a previous image stored in memory and storing the current image with the one or more panoramic parameters in memory are performed.

Abstract: An image processing system which processes, in real time, multiple images, which are different views of the same object, of video data in order to match features in the images to support 3 dimensional motion picture production. The different images are captured by multiple cameras, processed by digital processing equipment to identify features and perform preliminary, two-view feature matching. The image data and matched feature point definitions are communicated to an adjacent camera to support at least two image matching. The matched feature point data are then transferred to a central computer, which performs a multiple-view correspondence between all of the images.

Abstract: An image processing system and method for smoothing irregularities from 3D image information that was reconstructed from a plurality of 2D views of a scene, and particularly from homogeneous surfaces of objects in a scene. The method defines a window that overlaps a plurality of pixels of one of a plurality of 2D image views of a scene. Each pixel is associated with predefined 3D depth information, and further is associated with a matching curve. A subject pixel is located within the plurality of pixels overlapped by the window. The method calculates an average 3D depth information associated with the plurality of pixels overlapped by the window, and assigns the calculated average 3D depth information to the 3D depth information of the subject pixel, if the calculated average 3D depth information is within an error region of a matching curve associated with the subject pixel.

Abstract: An electronic circuit includes a selectively configurable differential signal interface and a selection control input for selecting one of a plurality of standard differential signal interfaces for configuration of the differential signal interface. The selection control input selects one of the following plurality of standard differential signal interfaces: reduced swing differential signaling (RSDS), low voltage differential signaling (LVDS), mini low voltage differential signaling (mini-LVDS), and bussed low voltage differential signaling (BLVDS), for configuration of the differential signal interface. The electronic circuit may also include a plurality of selectable voltage sources (611, 612, 613) and a plurality of selectable current sources (614, 615, 616, 617), for selecting, in response to an input signal at the selection control input, at least one of an operating D.C. voltage, a standard differential signal voltage, and a standard differential signal current for the differential signal interface.

Abstract: A closed loop delay line system (700) includes a phase lock loop that provides a phase lock output signal (715). A delay line (702) includes a clock input, a delay line output, and a delay line bias input. A bias signal provided to the delay line bias input (727) adjusts the speed of the delay line (702). A phase detector (720) compares phase between a first timing signal input (704) and the delay line output (706). A bias adjust circuit (726) mixes the phase compare output signal (725) and the phase lock output signal (715) to provide a combination bias signal (727) to the delay line (702). Additionally, the relative timing position of strobe outputs (734) from the delay line (702) can be individually adjusted.

Abstract: A self-timed data processing circuit module is provided. Data is provided to the data processing circuit along with a Req handshaking input. The data processing circuit has an isochronous processing delay for all data inputs. An example of a data processing circuit with isochronous processing delay is a One Hot Residue Number System arithmetic processing circuit. The data processing circuit processes the input data while the Req input propagates through a delay circuit that has substantially the same processing delay as the data processing circuit. Thus, the propagation delay of the Req signal is substantially equal to the data processing circuit's processing time. This allows the output of the delay circuit to be used to both latch the output of the data processing circuit and provide a “data ready” output.

Abstract: A method, system and computer readable medium for transforming three dimensional (3D) color information into a color standard is described. A 3D cube defined by eight RGB color points representing the eight vertices of the 3D cube is stored. Each of the eight points represents one of the colors: red, yellow, white, magenta, blue, black, green and cyan. In addition, each of the eight points represents the difference between the capacity of a display and the color standard. The 3D cube is divided into six tetrahedrons and the tetrahedron corresponding to an input RGB pixel is selected. A 3×3 matrix based on the vertices of the selected tetrahedron is calculated. The 3×3 matrix is then multiplied by the components of the input RGB pixel to produce an output RGB pixel conforming to the color standard.

Abstract: A modulo mi adder and a modulo mi,j scaling unit for use with an RNS. The adder includes a modulo mi barrel shifter, and a dynamic storage unit coupled to the barrel shifter to store the output of the barrel shifter. In a preferred embodiment, the dynamic storage unit includes one dynamic latch for each output line of the barrel shifter, with each of the dynamic latches including a clocked inverter in cascade with an inverter. One modulo mi,j scaling unit includes a modified modulo mi barrel shifter that performs both residue conversion and an arithmetic operation. The residue conversion is performed without using combinational logic. In one preferred embodiment, the modified barrel shifter performs the residue conversion though mi-mj additional columns that replicate normal columns for all modulo mi input lines that are congruent modulo mj.

Abstract: An electronic circuit includes a selectively configurable differential signal interface and a selection control input for selecting one of a plurality of standard differential signal interfaces for configuration of the differential signal interface. The selection control input selects one of the following plurality of standard differential signal interfaces: reduced swing differential signaling (RSDS), low voltage differential signaling (LVDS), mini low voltage differential signaling (mini-LVDS), and bussed low voltage differential signaling (BLVDS), for configuration of the differential signal interface. The electronic circuit may also include a plurality of selectable voltage sources (611, 612, 613) and a plurality of selectable current sources (614, 615, 616, 617), for selecting, in response to an input signal at the selection control input, at least one of an operating D.C. voltage, a standard differential signal voltage, and a standard differential signal current for the differential signal interface.

Abstract: An image processing system detects a plurality of image features in a first image corresponding to a first view of a scene, and a plurality of image features in a second image corresponding to a second view of the scene. The second image deviates from the first image as a result of camera relative motion. The system determines a two-view correspondence resulting in a potential match set having a maximum average strength of correspondence based at least in part on the total number of matching neighbor candidate image features. Additionally, a multiple-view correspondence between images results in a potential match set based at least in part on a computation of reprojection error for matched points that resulted from a projective reconstruction of the potential match set.

Abstract: A system includes a digital phase lock loop (PLL) constructed from an all digital circuit implementation and standard cell construction. The digital PLL includes a digital frequency synthesizer and a digital phase detector. The digital frequency synthesizer includes a digital DLL including a plurality of delay chains, each of the delay chains including at least one digitally programmable delay element for configuring the plurality of delay chains to achieve a phase lock with an input reference signal.

Abstract: A computing system includes a plurality of full adders that each receives a bit-wise inversion of a bit of a first data, a bit of a second data, and a bit of a third data, respectively, and provides a sum output and a carry output. An exclusive-OR logic module receives the sum output of a first of the plurality of full adders and a carry output of a second of the plurality of full adders and provides an exclusive-OR output. An AND logic module has a plurality of inputs and an AND output, wherein the exclusive-OR output is electrically connected to one of the plurality of inputs of the AND logic module, and the AND output provides a signal that indicates whether the first data equals the sum of the second data and third data.

Abstract: A method in a digital camera for image capturing at least two perspective images at a constant focal length from the digital camera, where both images share a common edge portion. The method including: recording a first image from a first perspective; displaying a preview of a second image from a second perspective; simultaneously with displaying the preview, presenting an overlapping edge region of the first image to allow alignment of the first image with the preview of the second image; and correcting the perspective of at least one image in an overlapping edge region. In an alternate embodiment, a digital camera and computer readable medium corresponding to the above method is described.

Abstract: A system for play-back of a still image comprising an image generator for generating a panoramic image by stitching together a plurality of images; memory space allocated for storing the panaoramic image generated by the image generator; and motion playback device (MPB) coupled to the memory space by address and data lines. The MPB comprises an input for receiving parameters for generating addresses to read the image for simulating the panning motion is a video camera scanning the image represented by the panoramic image along at least a first direction. In an alternate embodiment, a method and computer readable medium corresponding to the above system is described.

Abstract: A semiconductor package having an encapsulation that encapsulates an integrated circuit chip and an external lead frame for the chip. Multiple connection leads project from the periphery of the encapsulation. At least one external face of the encapsulation is covered with a layer of electrically conductive material, and the conducting material layer has at least one lateral extension that electrically contacts at least one of the projecting connection leads. A method of manufacturing such a semiconductor package is also provided.