Abstract: A switching I/O node for connection in a multiprocessor computer system. An input/output node switch includes a bridge unit and a packet bus switch unit implemented on an integrated circuit chip. The bridge unit may receive a plurality of peripheral transactions from a peripheral bus and may transmit a plurality of upstream packet transactions corresponding to the plurality of peripheral transactions. The packet bus switch may receive the upstream packet transactions on an internal point-to-point packet bus link and may determine a destination of each of the upstream packet transactions. The packet bus switch may further route selected ones of the upstream packet transactions to a first processor interface coupled to a first point-to-point packet bus link and route others of the upstream packet transactions to a second processor interface coupled to a second point-to-point packet bus link in response to determining the destination each of the upstream packet transactions.

Abstract: An apparatus for reordering packet transactions within a peripheral interface circuit. The apparatus includes a source tagging unit and a control unit. The source tagging unit may be configured to generate a plurality of tag values each corresponding to one of a plurality of packet commands. The control unit may include a first storage unit including a first plurality of locations and a second storage unit including a second plurality of locations. Each of the locations corresponds to one of the plurality of tag values. Each of the first plurality of locations may provide an indication of whether a given tag value corresponds to a first packet command in a given data stream. A first given location of the second plurality of locations corresponds to the tag value indicated by the first storage unit and stores a tag value of a second packet command in the given data stream.

Abstract: A tunnel device for an input/output node of a computer system. A tunnel device includes a first interface, a second interface and a control unit. The first interface may receive a plurality of data bytes associated with a command packet on a first external input/output bus. The second interface may be coupled to the first interface by an internal data path configured to convey up to a maximum number of data bytes in a given cycle. The control unit may be coupled to control the conveyance of the data bytes from the first interface to the second interface upon the internal data path. The first interface may further align the smaller number of data bytes on a corresponding number of designated bits of the internal data path with no intervening invalid data bytes when conveying a smaller number of data bytes than the maximum number of data bytes.

Abstract: A method and apparatus for manipulating work queue elements via a hardware adapter and a software driver. The software driver is configured to cause a plurality of work queue elements to be stored in a queue pair including a plurality of storage locations. Each of the plurality of storage locations includes an indicator indicating whether a corresponding work queue element has been completed. The hardware adapter is configured to select one of the plurality of storage locations and to service a corresponding one of the plurality of work queue elements, and in response to completion of a task associated with the corresponding work queue element, to cause the indicator to indicate that the corresponding work queue element has been completed. Additionally, the software driver is configured to cause a new work queue element to be stored in the selected storage location in response to detecting that the indicator indicates that the corresponding work queue element has been completed.

Abstract: A starvation avoidance mechanism for an input/output node of a computer system. A scheduler unit includes a first buffer circuit and a second buffer circuit. The first buffer circuit includes a first plurality of buffers for storing selected control commands received from a first source and the second buffer circuit includes a second plurality of buffers for storing selected control commands received from a second source. The scheduler further includes an arbitration circuit coupled to the first buffer circuit and to the second buffer circuit. The arbitration circuit may be configured to arbitrate between the control commands stored in the first buffer circuit and the control commands stored in the second buffer circuit. The outcome of selected arbitration cycles may be dependent upon a number of times in which a control command from a given one of the buffers is blocked due to an unavailable destination.

Abstract: A graphics subsystem including a RAMDAC for connection to a graphics bus implemented on an integrated circuit chip separate from a graphics processor. In one embodiment, the graphics processor is configured to render digital image information in response to graphics commands and to store the digital image information in a memory. The RAMDAC IC includes a conversion unit, which includes a color mapping unit and a digital-to-analog converter and is configured to convert a representation of the digital image information into one or more analog signals for driving a video display. The graphics subsystem further includes a Direct Memory Access (DMA) controller implemented on the second integrated circuit chip. The DMA controller is configured to generate read requests to retrieve the digital image information stored in the memory to thereby cause the digital image information to be provided to the conversion unit.

Abstract: An I/O node for a computer system including an integrated graphics engine. An input/output node is implemented upon an integrated circuit chip. The I/O node includes a first transceiver unit, a second transceiver unit, a packet tunnel, a graphics engine and a graphics interface. The first transceiver unit may receive and transmit packet transactions on a first link of a packet bus and the second transceiver unit may receive and transmit packet transactions on a second link. The packet tunnel may convey selected packet transactions between the first and the second transceiver unit. The graphics engine may receive graphics packet transactions from the first transceiver unit and may render digital image information in response to receiving the graphics transactions. The graphics interface may receive additional graphics packet transactions from the first transceiver unit and may translate the additional graphics packet transactions into transactions suitable for transmission upon a graphics bus.

Abstract: A buffer circuit for a peripheral interface circuit in an I/O node of a computer system. A buffer circuit includes a first buffer and a second buffer. The first buffer may be configured to store a plurality of selected packet commands within a plurality of storage locations. The second buffer is coupled to the first buffer and may be configured to store a plurality of index values. Each index value corresponds to one of the storage locations in the first buffer. The buffer circuit further includes a write logic circuit that is coupled between the first buffer and the second buffer. The write logic circuit may be configured to successively read each of the plurality of index values from the second buffer and to cause a selected packet command to be stored in each storage location corresponding to each of the plurality of index values within the first buffer.

Abstract: A buffer circuit for rotating outstanding transactions. A buffer circuit includes a buffer and a command update circuit. The buffer may be configured to store packet commands that belong to a respective virtual channel of a plurality of virtual channels. The packets may be stored in the buffer to await transmission upon a peripheral bus. Once a given packet is selected for transmission, a peripheral bus cycle corresponding to the given packet command may be generated upon the peripheral bus. The command update circuit may be configured to generate a modified packet command in response to receiving a partial completion indication associated with the peripheral bus cycle. The command update circuit may also be configured to cause the modified packet command to be stored within the buffer.

Abstract: A system and method for synchronizing mirrored and striped disk writes. A data storage system may include a client computer system coupled to a first data storage device and a second data storage device and configured to transmit a first data write request. The first storage device may be configured to transmit a sequence number to the client computer system in response to receiving the first data write request. The client computer system may be further configured to transmit a second data write request including the sequence number to the second storage device. The second data storage device may include a counter and is configured to compare a current counter value to the sequence number. If the counter value is equal to the sequence number, the second storage device stores the data bytes corresponding to the second data write request and increments its counter.

Abstract: An apparatus is described in which the locations of a buffer are used to store a plurality of control packets received in a node, wherein the plurality of control packets belong to a plurality of virtual channels. The number of locations assigned to each virtual channel may be dynamically allocated. The number of locations allocated to each virtual channel may be determined by an update circuit. Count values corresponding to the number of locations allocated to each virtual channel may then be stored within a programmable storage, such as a register, for example. The count values may be subsequently copied into a slave register and incremented and decremented as locations become available and notifications corresponding to the available locations are sent, respectively.