Abstract: Mechanisms are provided for modeling a plurality of devices of an integrated circuit design as a single statistically equivalent wide device. An integrated circuit design is analyzed to identify a portion of the integrated circuit design having the plurality of devices. For the plurality of devices, a statistical model of a single statistically equivalent wide device is generated which has a statistical distribution of at least one operating characteristic of the single statistically equivalent wide device that captures statistical operating characteristic distributions of individual devices in the plurality of devices. At least one statistical operating characteristic of the single statistically equivalent wide device is a complex non-linear function of the statistical operating characteristics of the individual devices. The integrated circuit design is modeled using the single statistically equivalent wide device.

Abstract: Mechanisms for ensuring data consistency in a data store are provided. The mechanisms access a parity scrub factor f and perform a check on a data group of the data store. The check on the data group includes performing a parity check on a portion of the data group, the portion being equal to 1/f of the data group, and performing a data verify on the remainder of the data group. The performing of the check is repeated for the entire data store. An offset factor is used to select the portion of the data group for the parity check. In this case, the offset factor may be incremented when the performance of the check on the data group of the data store has been repeated for the entire data store.

Abstract: Mechanisms for accessing a set associative cache of a data processing system are provided. A set of cache lines, in the set associative cache, associated with an address of a request are identified. Based on a determined mode of operation for the set, the following may be performed: determining if a cache hit occurs in a preferred cache line without accessing other cache lines in the set of cache lines; retrieving data from the preferred cache line without accessing the other cache lines in the set of cache lines, if it is determined that there is a cache hit in the preferred cache line; and accessing each of the other cache lines in the set of cache lines to determine if there is a cache hit in any of these other cache lines only in response to there being a cache miss in the preferred cache line(s).

Abstract: Mechanisms are provided for replicating transactions at a source database node on a target database node of the data processing system. A transaction message, for a transaction, is stored in a receive queue data structure of the target database node. An agent thread applies a change to data of the target database node based on a specification of the change in the transaction message. An identifier of the transaction message is stored in a done message data structure of the target database node and the identifier of the transaction message is also stored in a prune queue data structure of the target database node. A prune thread determines if a contiguous range of identifiers of transaction messages equal to or greater than a predetermined batch size is present in the prune queue data structure. If so, then a range of transaction messages is deleted from the done message data structure.

Abstract: Methods and arrangements of representing the allocation of integers are discussed. Embodiments include transformations, code, state machines or other logic to represent the allocation of integers. An embodiment may involve representing a first allocation of integers via a set of nodes of a tree. In the representation, a data structure in a node may represent, for each integer in a set of integers, whether the integer is allocated or free. The embodiment may also involve representing a subsequent allocation. The representing may include adding a new node to the nodes of the tree for the first allocation. The subsequent allocation may consist of freeing of an integer allocated in the first allocation. The data structure of the new node may represent that the integer is free.

Abstract: Mechanisms for evaluating software sustainability are provided. The illustrative embodiments provide code scanning tools for identifying authors of portions of a software product and various attributes about the development, maintenance, and improvement of portions of the software product over time. This information may be correlated with organizational information to identify portions of the software product that may be lacking in sustainability by the persons currently associated with the software organization. Moreover, this information may be used to obtain information regarding the relative quality of the composition or conception of portions of the software product, portions of the software product that have required a relatively larger amount of resources to develop over time, a relative indication of which portions of the software product are “harder” or “easier” to sustain and who is associated with those portions of the software product, and the like.

Abstract: Mechanisms are provided for processing streaming data at high sustained data rates. These mechanisms receive a plurality of data elements over a plurality of non-sequential communication channels and write the plurality of data elements directly to the file system of the data processing system in an unassembled manner. The mechanisms further perform a data scrubbing operation to determine if there are any missing data elements that are not present in the plurality of data elements written to the file system and assemble the plurality of data elements into a plurality of data streams associated with the plurality of non-sequential communication channels in response to results of the data scrubbing indicating that there are no missing data elements. In addition, the mechanisms release the assembled plurality of data streams for access via the file system.

Abstract: Mechanisms are provided for analyzing and optimizing loops with conditional control flow in source code based on array reference safety. Mechanisms are provided for analyzing blocks of the source code to identify a conditional control flow loop having loop source code specifying a total access range for an array reference. A safe access range, of the total access range of the array reference in the loop source code, is identified over which a compiler-based optimization of the loop source code can be safely applied without introducing new exception conditions. The compiler-based optimization of the loop source code is performed based on the identified safe access range to generate optimized code. The optimized code is output for generation of executable code for execution on a processor.

Abstract: A log file is secured. One implementation involves maintaining a log file including one or more log entries in a storage device connected to a computer, and entering a new log entry by generating a new message authentication code based on a preceding log entry including a preceding message authentication code, and applying the message authentication code to the new log entry.

Abstract: A method and system for dynamically sharing performance information among multiple computing nodes. One implementation involves dynamically obtaining performance information from deployments of an information technology (IT) product/solution at said computing nodes, and transmitting the obtained performance information to a server over a communication network for storing the obtained performance information in a knowledge database. The server operates to dynamically determine new configuration information based on the information in the database, store the new configuration in the database, and provide the new configuration information to said deployments by transmitting the new configuration information over the network.

Abstract: An example of a solution provided here comprises receiving as input at least one event (chosen from an event generated by an application probe, and an event generated by a component probe), and providing graphical output based on the inputs, whereby a user correlates a component problem with a performance problem affecting an application. Methods connected with graphics for end to end component mapping and problem-solving in a network environment, systems for executing such methods, and instructions on a computer-usable medium, for executing such methods, are provided.

Abstract: Mechanisms are provided for providing hardware based dynamic load balancing of message passing interface (MPI) tasks by modifying tasks. Mechanisms for adjusting the balance of processing workloads of the processors executing tasks of an MPI job are provided so as to minimize wait periods for waiting for all of the processors to call a synchronization operation. Each processor has an associated hardware implemented MPI load balancing controller. The MPI load balancing controller maintains a history that provides a profile of the tasks with regard to their calls to synchronization operations. From this information, it can be determined which processors should have their processing loads lightened and which processors are able to handle additional processing loads without significantly negatively affecting the overall operation of the parallel execution system. Thus, operations may be performed to shift workloads from the slowest processor to one or more of the faster processors.

Abstract: Hybrid caching techniques and garbage collection using hybrid caching techniques are provided. A determination of a measure of a characteristic of a data object is performed, the characteristic being indicative of an access pattern associated with the data object. A selection of one caching structure, from a plurality of caching structures, is performed in which to store the data object based on the measure of the characteristic. Each individual caching structure in the plurality of caching structures stores data objects has a similar measure of the characteristic with regard to each of the other data objects in that individual caching structure. The data object is stored in the selected caching structure and at least one processing operation is performed on the data object stored in the selected caching structure.

Abstract: Mechanisms are provided for collaborating between two or more operating system image repository systems. A first operating system image (OSI) repository system is associated with a second OSI repository system. Each of the first and second OSI repository systems store one or more OSIs for use either natively or virtually by client computing devices. One or more collaboration rules are defined that define a manner by which OSI information in the first OSI repository system is shared with the second OSI repository system. A collaborative operation is performed between the first OSI repository system and the second OSI repository system. An extent of the collaborative operation is circumscribed by application of the one or more collaboration rules.

Abstract: Mechanisms are provided for detecting changes in virtual storage device configurations. The mechanisms detect an event corresponding to a change in configuration of a virtual storage device. The virtual storage device is comprised of a plurality of portions of a plurality of physical storage devices. The mechanisms further, in response to detecting the event, determine if the change in configuration of the virtual storage device results in a change in the types of physical storage devices that are part of the virtual storage device. Moreover, the mechanisms further transmit a notification, in response to a determination that the change in configuration of the virtual storage device results in a change in the types of physical storage devices that are part of the virtual storage device, of the results of the change in configuration of the virtual storage device to one or more registered recipients registered to receive such notifications.

Abstract: Mechanisms for providing to a plurality of WPARs private access to physical storage connected to a server through a VIOS are disclosed. In one embodiment, a server is logically partitioned to form a working partition comprising a WPAR manager and individual WPARs. Each WPAR is assigned to a different virtual port. The virtual ports are created by using NPIV protocol between the WPAR and VIOS. Thereby, each WPAR has private access to the physical storage connected to the VIOS.

Abstract: A recursive logical partition real memory map mechanism is provided for use in address translation. The mechanism, which is provided in a data processing system, receives a first address based on an address submitted from a process of a currently active logical partition. The first address is translated into a second address using a recursive logical partition real memory (RLPRM) map data structure for the currently active logical partition. The memory is accessed using the second address. The RLPRM map data structure provides a plurality of translation table pointers, each translation table pointer pointing to a separate page table for a separate level of virtualization in the data processing system with the data processing system supporting multiple levels of virtualization.

Abstract: Providing access to a shared resource in a computing environment involves maintaining a timestamp for each shared resource, the timestamp representing the time the resource was last accessed. Then, detecting if the resource is reserved before obtaining access to the resource, by reading the resource timestamp, and if the timestamp represents a future time relative to the current time, indicating that the resource is reserved and delaying access to the resource. If the resource is unreserved, then accessing the resource by reading the resource timestamp to detect any changes in the timestamp since the last reading; if unchanged, then accessing the resource. If the resource is unreserved, then obtaining exclusive access to the resource by reserving the resource by incrementing its timestamp by a reservation period; accessing the resource; and resetting the resource timestamp to the current time.

Abstract: Mechanisms are provided, for implementation in a data processing system having at least one physical processor and at least one associated cache memory, for allocating cache resources of the at least one cache memory to virtual processors of the data processing system. The mechanisms identify a plurality of high priority virtual processors in the data processing system. The mechanisms further determine a percentage of cache lines of the at least one cache memory to be assigned to high priority virtual processors. Moreover, the mechanisms mark a portion of the cache lines in the at least one cache memory as being evictable by only high priority virtual processors based on the determined percentage of cache lines to be assigned to high priority virtual processors. The marked portion of the cache lines cannot be evicted by lower priority virtual processors having a priority lower than the high priority virtual processors.

Abstract: An apparatus is provided that comprises a plurality of signaling planes providing signal pathways and at least one internal reference plane providing either a voltage or a ground connection. The at least one internal reference plane are provided between at least two of the signaling planes. The apparatus further comprises a signal blind/buried via coupling a signal pathway of a first one of the at least two signaling planes with a signal pathway of a second one of the at least two signaling planes. The blind/buried via runs through the at least one internal reference plane. The apparatus also comprises at least one first conductive feature in the first one of the at least two signaling planes. The at least one first conductive feature is in close proximity to the signal blind/buried via and increases the capacitive coupling of currents in the reference planes of the apparatus.