Abstract: A memory system having a read/write head is provided wherein a system clock or a test clock can be used to initiate a pulse for enabling the read/write head during a write period and a delay circuit coupled to the system clock or to the test clock can be used to terminate the enabling or control pulse, with a write clock having an input coupled to the system clock also used to terminate the enabling or control pulse during a write period.
Type:
Grant
Filed:
August 31, 1994
Date of Patent:
June 25, 1996
Assignee:
International Business Machines Corporation
Inventors:
David B. Grover, Edward F. O'Neil, III, Robert A. Ross, Jr.
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