Abstract: Coherent phase recovery in a time division multiple access (TDMA) system can be attained in a novel manner. After symbol-timing and frequency-offset are estimated, the stored received phase at the desired sampling instant is gated from memory and fed to the input of the carrier phase recovery circuitry. During a first half portion of a burst, the first half portion of the burst is stored, while the loops acquire lock. The first half portion is then fed to one of the loops in a reverse order of its reception. Demodulation is initiated as a common state of both loops in a mid-portion of the signal burst. The previously stored first half portion is backwardly demodulated by one of the loops, while the other loop demodulates the second half portion of the burst. The whole burst is recovered by storing the demodulated first and second half portions in random access memory, and then reordering the stored demodulated burst by reading the memory backwards for the first portion.

Abstract: A short optical pulse generator is disclosed in which the optical radiation from a driven laser diode (101) is coupled to an external cavity which includes a looped directional coupler (104, 120) which reflects a portion of the optical radiation back to the laser causing the laser to mode-lock and produce an output which consists of a stream of very short high repetition optical pulses. By changing the length of the loop (107), the repetition rate of the pulse stream can be varied and by adjusting the coupling coefficient of the coupler either mechanically or electrooptically, the pulse width and pulse height parameters of the pulse stream can be varied.

Abstract: A digital phase locked loop operable over a wide dynamic range has jitter performance that is exactly bounded within predetermined limits. The phase locked loop includes an accumulator-type digital voltage controlled oscillator (201) which generates from a high speed system clock, an output clock signal at frequency equal to p times the frequency of an input clock signal, and which output frequency is controlled by the value k of a digital input to the VCO. A frequency window comparator (208) compares the number of output clock pulses between input clock pulses to determine, based on the count, whether the frequency of the output is too high, too low or equal to the correct frequency. A phase window comparator (210) simultaneously determines from the phase of the output clock signal whether the phase is leading, lagging or within a prescribed window of acceptability.

Abstract: In order to correctly demodulate a received sequential burst of symbols in a Time Division Multiple Access (TDMA) radio system, proper symbol timing is necessary. A method and circuitry for estimating symbol timing is disclosed in which the IF radio signal is sampled and digitized at a sampling rate which is sixteen times the symbol rate. The digitized samples are processed to obtain phase values. A one symbol delay is introduced and differential phase values derived, a differential phase value being derived for each of the sixteen sampling times per symbol. The differential phase values are compared with expected differential phase values and the absolute differences are accumulated for each sampling time over substantially the entire burst. The symbol timing is selected to be the particular one-of-the-sixteen sampling times that results in the minimum sum of differences.

Abstract: At the transmitting end of an optical transmission system, a wide linewidth LED (31) is intensity modulated by a first digital information signal and a narrow linewidth DFB (Distributed Feedback) laser (32) is frequency modulated by a second digital information signal and the two modulated optical signals are combined (33) for transmission over a single mode optical fiber (34). At the receiving end, the intensity modulating digital signal is recovered from the received optical signal by a photodetctor (52). The frequency modulating digital signal is recovered by a coherent receiver (53) which includes a local oscillator (55) the output of which is optically combined (54) with the received optical signal. A photodetector (56) converts this combined optical signal to an electrical IF signal, and an IF demodulator (57) reconstructs the second digital signal therefrom.

Abstract: An improved low bit-rate interframe video encoder is disclosed of the type known as a hybrid coder. A hybrid coder achieves image compression by using a two-dimensional signal transformation on blocks of differential pel data in the forward loop of a DPCM coder. The transform coefficients of each block are then quantized and entropy coded for transmission. Coding efficiency is in part determined by the size of the transform block. Larger blocks are more bit efficient because of the lower quantity of overhead data required, but require a complex transformer hardware implementation. In addition, larger blocks produce annoying block distortion. The disclosed coder has the advantages of both large and small block size division of the video image. In the disclosed coder, after differential combination (307) with a corresponding block from the previous frame, each m.times.m block of pel data is sub-divided (309) into smaller n.times.

Abstract: The circuit phase aligns a phase-varying input data stream with a local clock. The data stream is sampled at the 0.degree. and 180.degree. phases of the local clock. Two pairs of outrigger samples which closely bracket the aforementioned primary samples are also obtained by the sextet sampler. Adjacent pairs of the six samples are applied to Ex-Or gates to yield disagreement signals which indicate the locations of data transitions relative to the samples. The primary samples (0.degree. and 180.degree.) are serially loaded into different halves of a biphase register, the taps of which provide the output with differently delayed versions of the input data at either 0.degree. or 180.degree.. A control circuit analyzes the disagreement signals and provides control signals to a counter which determines which of the biphase register taps is connected to the output. The output is a replica of the input which is synchronized with the local clock.

Abstract: In a circuit that detects from a received RF signal the digital signal modulated on the IF carrier signal by recovering the unmodulated IF carrier signal and comparing the recovered IF carrier with the downconverted RF signal, improvements are presented which minimize errors due to rapid and large phase changes in the RF signal. The circuit includes a downconverter (104) for downconverting the received RF signal to the IF level and a phase-locked loop (115, 118, 116, 119, 117) for both providing correction for relatively slow variations in the RF signal and for deriving the recovered IF carrier signal to which the downconverted IF signal is compared (108). Large and rapid phase changes in the RF signal are detected in a separate loop in the phase locked loop by monitoring (122) the sign and phase of the phase locked loop error signal for signals exceeding a predetermined threshold and rapidly advancing (123) or retarding (124) the phase of the recovered IF carrier whenever the threshold is exceeded.

Abstract: The laser driver circuit of the invention stabilizes the low operating output power level of a laser (301) modulated by a digital input signal, at a fixed preset value L.sub.o, by automatically adjusting the bias current, I.sub.b, supplied to the laser to compensate for variations in the laser threshold due to temperature changes and aging. The circuit includes a fast photodetector (401) which is responsive to the modulated light output of the laser. The photodetector output is combined (306, 308) with a data sensitive reference signal (i.sub.r) and a preset level setting input signal (i.sub.o) which is equal to .eta. times the desired low operating output power level L.sub.o, where .eta. is the coupling coefficient of the photodetector. Reference signal i.sub.r varies in accordance with the input data between a zero value when the input is ZERO and a value equal to what is estimated to be the photodetector output due to the data modulation when the input is ONE.

Abstract: The broadband semiconductor optical amplifier fabricated in accordance with the teachings of the present invention comprises first and second active semiconductor regions (50, 51) disposed in tandem with each other, and means for injecting current (I.sub.1,I.sub.2) into the first and second active semiconductor regions to provide gain distributions over wavelength regions in the two active semiconductor regions which partially overlap to form a combined gain distribution over a wider range of wavelengths. Anti-reflection coatings (54, 55) are disposed on the extreme ends of the combined structure. Tuneable wavelength selective amplification over the wider range is achieved in various embodiments by including a tunable optical bandpass filter (53) or by including various tunable auxiliary light guiding structures (115, 116; 140; or 450) to which and from which light power is coupled from and to the active semiconductor regions of the amplifier, respectively.

Abstract: This processor is capable of real time processing of blocks of video pixel or other two-dimensional data to yield the two-dimensional Discrete Cosine Transform (DCT) thereof. The processor can be used as part of a video bandwidth or image compression system. The circuitry comprises a first one-dimensional DCT processor which simultaneously computes an entire row or column of vector inner products by using distributed arthmetic and using decimation-in-frequency to reduce the amount of memory capacity (ROM) required. Partial sums may also be used to further reduce ROM size. The one-dimensional transformed matrix from the first processor is stored in a transposition memory and the transpose of the stored matrix is applied to a second one-dimensional DCT processor of similar circuitry which computes the desired two-dimensional DCT of the input data matrix.

Abstract: A Phase/Frequency Locked Loop comprises a controllable oscillator which is phase locked with the clock of an incoming non-return-to-zero digital data signal. The controllable oscillator may be a voltage-controlled oscillator (VCO) or may be purely digital. The circuitry includes a novel digital phase and frequency detector which detects both frequency and phase error by sampling the incoming data stream at multiple phases of the output of the VCO (or the digital equivalent thereof). One of two binary disagreement signals are produced depending on the sense of the phase error. During periods of frequency error, the circuit automatically selects the proper type of disagreement signal (the leading-edge disagreement) required to achieve frequency lock.

Abstract: In order to determine whether defects are present in a semiconductor device (103) biased to its normal operating levels, a scanning electron microscope (101) equipped with an electron beam blanker (102) scans the device with a pulsed electron beam. Charge carriers generated within the device in response to each pulse of electrons are collected and amplified by a charge carrier sensitive preamplifier (114) to produce a voltage signal which when applied to a CRT (118) produces an image of the semiconductor. Defects in the device can be located from irregularities in the image and the presence of bias dependent defects can be ascertained by varying the bias current supplied (113) to the device and noting changes in the image.

Abstract: This circuit phase aligns a phase-varying input data stream with a local clock. The incoming data stream is sampled at four quadrature points and these samples are applied to Ex-Or gates to yield four disagreement signals which indicates whether or not a transition from binary 0 to 1, or vise versa, has occurred between any pair of samples. The in-phase (0.degree.) and anti-phase (180.degree.) samples are serially loaded into different but similar shift registers, the taps of which provide the output with earlier or later versions of the input data stream at either 0.degree. or 180.degree.. A control circuit analyzes the disagreement signals and provides control signals which determine which of the shift register taps is connected to the aligner output. The circuit can correct for phase slippage between input data and local clock of up to plus or minus several time slots.

Abstract: In order to multiplex a plurality of various rate subchannels onto a fixed rate channel, a frame structure is defined consisting of j tuples of bits. Some of the tuples are i bits long and some are less than i, the sum of the bits less than i in these tuples being equal to k where k is greater than or equal to zero. The total number of bits per frame is thus equal to ij-k where i, j and k are mathematically determined as a function of the rates of the subchannels and the rate of the fixed channel. In one tuple of i bits in each frame, all bits are set ZERO. In each other tuple, the last bit is set ONE. Framing is detected by monitoring for a ONE followed by i ZEROes a pattern which cannot occur elsewhere in the frame regardless of the data. This frame arrangement can yield shorter frames than the frame structure disclosed in U.S. Pat. No. 4,617,658, thus decreasing reframe time.

Abstract: A telecommunications interface is disclosed. The inventive telecommunications interface is capable of collecting multiple asynchronous video, audio, graphic and data signals from a variety of different kinds of sources and retransmitting such signals in a suitable form for display or detection with one or more types of receiver equipment at one or more locations. The interface operates at rates ranging from several hundred bits per second to several gigabits per second.The telecommunications interface includes a dual port RAM whose input and output operate asynchronously. Signals from the user sources are stripped of timing and source identification information and are written into the dual port RAM, while output processors read previously stored user signals out from the dual port RAM. The output processor appropriately format the retrieved signals, which are then transmitted to the receiver equipment.

Abstract: Longitudinal mode coupling is used in an injection laser to achieve single longitudinal mode output. By imposing a to small amplitude sinusoidal signal to modulate the laser injection current, this coupling is provided by producing sidebands on the photon distributions of the longitudinal modes.

Abstract: A synchronous PCM digital transmission system including multilevel multiplexing wherein the higher order multiplexers interleave two or more tributary signals each of which comprises a multiplexed plurality of subtributaries. Multiplexer framing is achieved by means of an auxiliary frame pattern or byte, F.sub.T, which is slidable within the subscriber-defined frames. Each multiplexer in the system re-frames or slides F.sub.T and its associated overhead so that the F.sub.T bytes at each multiplexer are synchronized. The F.sub.T bytes can be used to frame or synchronize scrambling and de-scrambling circuitry. This concept provides multiplexer framing and yields high-speed multiplexed signals which are all exact multiples of the system clock rate, using relatively simple circuitry compared to competitive designs.

Abstract: A Mach-Zehnder interferometric modulator includes on a Z-cut crystal substrate of LiNbO.sub.3 an input waveguide section (302), an input branching section (303) for dividing an optical signal on the input waveguide into two substantially equal portions, first and second branch waveguides (304, 305) each having an electrode associated therewith (309, 308), an output branching section (306) for recombining the light from each branch waveguide into a single optical signal on an output waveguide section (307). The two branch waveguides are spaced close enough to maximize the field overlap between the applied electrical field and the optical field in the waveguides but are optically decoupled to prevent cross-coupling of light between the branches. This decoupling is achieved by using structures which change the propagation constant of one of the branches with respect to the other along the modulation length.

Abstract: An injection laser fabricated in accordance with the teachings of the present invention comprises a laser cavity having first and second active laser regions disposed in tandem therein, means for injecting current into the first and second active laser regions to provide gain distributions over wavelength regions in the two active laser regions which partially overlap to form a combined gain distribution over a range of wavelengths and means for providing wavelength within the range. In various embodiments of the present invention, the means for providing wavelength selective reflector or means for coupling energy out of the active regions. Moreover, the wavelength of the output radiation in various embodiments is determined by the values of the injected current density in the two active laser regions and the relative magnitudes of the loss at specific wavelengths.