Abstract: An improved optical apparatus and system for producing a three-dimensional real image of an object. The apparatus includes a support member, a first concave reflective surface affixed to the support member and having an associated focal length, and a second concave reflective surface affixed to the support member. The first concave reflective surface and the second concave reflective surface are placed in substantially fixed spatial relationship to each other to define an acute angle so that when the object is appropriately placed further than the focal length of the first concave reflective surface, the apparatus produces a three-dimensional real image of the object.

Abstract: Input/output and local area network functions are combined into a single integrated circuit on a single semiconductor (e.g., a single piece of silicon). Preferred system embodiments on a single integrated circuit are typically placed inside a host system (e.g., a personal computer based on Intel.RTM.'s 286, 386, 486, and Pentium microprocessors) and interrelate with standard operating systems (e.g., Microsoft.RTM.'s DOS, IBM.RTM.'s OS/2) on traditional, commonly used bus architectures (e.g., Industry Standard Architecture and Enhanced Industry Standard). Local area network circuitry and input and output circuitry are both coupled to at least one host system (and indirectly to potentially any number of host systems tied together via the local area network system) via a common data bus. The input and output circuitry couples the host system to at least one input/output channels.

Abstract: A video image frame consisting of a two-dimensional array of picture elements (pixels) is decomposed into a set of rectangular image portions (tiles). Within each tile, variance between pixel intensity values is less than a predetermined value. A tile is encoded by a value set identifying the tile and including a single intensity value for all pixels in the tile. Frame-to-frame variation of the video image is encoded by inter-frame tile comparison and encoding of sub-tiles representative of change from a previous frame to a current frame.

Abstract: A test access port (TAP) controls monitoring and testing of static current IDDQ in integrated circuit (IC) devices having both a TAP of the type specified in IEEE Standard 1149.1 Test Access Port and Boundary Architecture and built-in current (BIC) monitors. BIC monitors are coupled between MOS or CMOS modules of the IC device and the low potential power rail (GND) for monitoring static current IDDQ. Bypass or shunt MOS transistors (N1,N2, . . . , NN) are coupled with primary current paths in parallel with the respective BIC monitors between the CMOS circuit modules and low potential power rail (GND). The TAP data registers (TDR's) include a design specific BIC shunt control TDR (BICSC TDR) constructed for receiving a coded BIC monitor bypass code (BICBC) at the TDI pin. BICSC TDR outputs are coupled to control nodes of the respective MOS bypass transistors (N1,N2, . . . , NN) for controlling the conducting state of the bypass transistors according to the BICBC.

Abstract: In a bipolar or BiCMOS process, a heavily doped buried layer of a first conductivity type and a heavily doped channel stop region of a second conductivity type are formed in a lightly doped substrate of the second conductivity type. A lightly doped epitaxial layer of the first conductivity type is grown. An implant of the first conductivity type creates a guard ring around the bipolar transistor active region and also creates a higher-doped collector region inside the active region. In the BiCMOS process, during the formation of CMOS wells, a silicon nitride mask over the bipolar transistor inhibits oxidation of the epitaxial layer and the oxidation-enhanced diffusion of the buried layer. As a result, the epitaxial layer can be made thinner, reducing the collector resistance. The MOS transistor wells can be formed without an underlying buried layer, simplifying the process and decoupling the bipolar and MOS transistor characteristics from each other.

Abstract: Two dimensional data structures are represented by quadtree codes with embedded Walsh transform coefficients. The quadtree code permits both variable block size inherent in quadtrees, and the calculational simplicity of Walsh transform descriptions of nearly uniform blocks of data. Construction of the quadtree is calculationally simple for implementation in a digital system which does a bottom-up determination of the quadtree because Walsh transform coefficients and a measure of the distortion can be recursively calculated using only Walsh transform coefficients from the previous level in the quadtree. Uniform step size quantization, which is optimal for variable length coding and generalized gaussian distributions, permits fast encoding and decoding of quadtree code.

Abstract: An electrostatic discharge protection (ESDP) transistor element is coupled at an input or output of an MOS integrated circuit (IC) device for protecting internal transistor elements of the MOS IC device from electrostatic discharge (ESD) dielectric breakdown voltages. A relatively thick passivating layer of low temperature deposited passivating material is deposited over the active area between the channel and gate of the ESDP transistor element. A metal layer gate is formed over the passivating layer. The channel insulating layer thickness provides a turn on voltage V.sub.TON less than the dielectric breakdown voltage BVGOX of internal transistor elements. The bond pads of the MOS IC device are used for the metal layer gates and the metal layer gate bond pads are formed over the active area of the ESDP transistor elements.

Abstract: A multiple-gap head for transferring data to or from a storage medium is disclosed. Data read by the gaps are directed over a plurality of serial data paths where the data are processed and synchronized. In some embodiments, all or part of a data synchronizer is shared by the serial data paths. The data are then assembled into a parallel data stream for delivery to a computer. Reading the data simultaneously with multiple gaps increases by several times the rate at which data can be transferred to or from a storage medium. In accordance with another aspect of the invention, a three-gap head is provided to reduce or eliminate the cross-talk or noise fringe problems which reduce the track density in a storage medium. A signal attenuator and a signal inverter are connected to each of the side gaps and the outputs thereof are summed with the signal originating at the center gap, such that the inverted signals from the side gaps cancel any cross-talk originating at the center gap.

Abstract: In a BiCMOS process, a gate oxide is grown over the MOS transistors and over the base regions of the bipolar transistors. The base is implanted through the gate oxide and, in some embodiments, through a thin polysilicon layer overlying the base oxide. Then an opening is etched over the base regions in the thin polysilicon layer and the gate oxide, another polysilicon layer is deposited, and the two polysilicon layers are patterned to provide emitter contact regions and gate regions. The polysilicon etch terminates on the gate oxide. After an LDD implant or implants, an insulating layer is deposited and etched anisotropically to create spacers on the sidewalls of the emitter contact regions and the gate regions. During the etch, the gate oxide is etched away around the spacers to expose the extrinsic base regions and the source and drain regions.

Abstract: A semiconductor integrated circuit device is provided with an electrical interconnect system which is stable at high temperatures. The interconnect system employs refractory metal compounds which are electrically conductive, which form stable couples with silicon and compounds thereof, and which remain stable at temperatures exceeding approximately 500.degree. C.

Abstract: The first electrical switch contact of an electrostatic switch is formed over a substrate. A layer of electrically insulating material is interposed between the first switch contact and the substrate where the substrate is a silicon substrate having active regions. In that case, contact holes are formed in the insulating layer where desired to form electrical contact between the first switch contact and an underlying active region. An electrically insulating layer is formed over the first switch contact. A second switch contact is formed over the electrically insulating layer in a position such that a middle portion of the second electrical contact overlies a middle portion of the first electrical contact. A void is then created between the middle portions of the two electrical contacts by removing a portion of the electrically insulating material there between.

Abstract: A P-channel floating-gate MOS transistor is used to detect and measure positive mobile ions in the oxide layers of a semiconductor device. The transistor is first "programmed" by applying a voltage close to the breakdown voltage of the transistor, which causes electrons to tunnel through the oxide underlying the floating gate and to become trapped on the floating gate. This results in a negative voltage on the floating gate, which turns the transistor on and causes a first current, I.sub.DS0 to flow through the transistor. The semiconductor device is then baked, or heated, to accelerate the movement of positive mobile ions attracted to the negative charge previously trapped on the floating gate. Any positive mobile ions collected by the floating gate will neutralize a portion of the negative charge on the floating gate and will create a less negative voltage on the floating gate, resulting in a lesser current through the device after the bake.

Abstract: In a bipolar transistor, the collector and the base are formed in an isolation region laterally bounded by a field insulator. The isolation region corners are spaced far from the emitter to reduce the collector-emitter leakage current. The base does not extend laterally throughout the isolation region. Thus the base is small and the collector-base capacitance is small as a result. Those corners of the isolation region that are not covered by a base contact region are covered and contacted by an insulator. This insulator prevents the field insulator from being pulled back during wafer clean steps. Consequently, the field insulator does not expose the collector. Further, the insulator covering the corners prevents the metal silicide on the surface of the extrinsic base from contacting the corners. The insulator overlying the corners thus reduces the collector-base leakage current.

Abstract: A design layout sequence for an application specific integrated circuit such as a gate array includes a schematic capture step, which results in a logic netlist file, and a placement and routing step which results in a number of various files defining, for example, bias drivers, I/O macros, and relationships between chip pads and I/O signals. The design layout sequence culminates in a physical data base file. The connectivity of this physical data base file is checked by first generating a circuit level netlist file for the entire option, and then comparing the circuit level netlist with the physical data base file. In generating the circuit level netlist file, information is obtained from the logic netlist file, as well as from some of the other files created in the design-layout sequence. In addition, basic information from which the circuit level netlist is constructed is obtained from a skeleton file library and a subcircuit library.

Abstract: A tristate output buffer circuit provides overvoltage protection from voltage signals on a common bus having a higher voltage level than the internal high potential power rail of the tristate output buffer circuit. A high potential level pseudorail (PV) is coupled to the NWELL of a P channel output pullup transistor (P4). A comparator circuit (P5,P6) couplings the pseudorail (PV) to the output (VOUT). The comparator circuit passgates (P5,P6) are constructed to couple the pseudorail (PV) to the high potential power rail (VCC) for VOUT<VCC and to couple the pseudorail (PV) to the output (VOUT) for VOUT>VCC. A feedback transistor (P1) couples the pseudorail (PV) to an internal node of the tristate output buffer circuit at the control gate node of the output pullup transistor (P4). The feedback transistor (P1) control gate node is coupled to a tristate enable input (EN) for turning on the feedback transistor (P1) during the tristate operating mode and holding off the output pullup transistor (P4).

Abstract: A number of dielectrically isolated single crystal islands are formed by implanting neon or other group Zero ions into a semiconductor substrate, preferably silicon, at a sufficiently high energy to created an amorphized region in the interior of the substrate, without excessively damaging the substrate surface through which the ions pass. The amorphized regions are highly resistive, and are suitable for isolation in some applications. Where better isolation is desired, a dielectric isolation structure is formed as follows. Trenches are formed down into the amorphized regions, and the substrate is heavily oxidized to convert the amorphized regions into buried oxide regions and the island sidewalls into oxide. The islands are made thicker by removing the oxide from the islands' top surfaces and sidewalls, and growing epitaxial silicon over the substrate. Second trenches are formed down to the buried oxide regions, and the substrate is again oxidized to convert the islands' sidewalls to oxide.

Abstract: Low-cost apparatus and method for achieving a moderately-precise resistance value into an integrated circuit without the use of resistive trimming or complex feedback loops. The invention has direct application to the production of integrated BiCMOS circuits making use of Delay Lines and/or Voltage-Controlled Ring Oscillators where a .+-.10% tolerance in delay time or frequency is acceptable. When incorporated into a PLL, it also presents advantages where tighter tolerances are required, because of its low inherent jitter. By the use of a single off-chip component, this invention overcomes variations in the operating circuit otherwise arising from chip fabrication irregularities, power supply voltage fluctuations, and ambient temperature drift. In the Preferred Embodiment of the present invention, the resistive element is used as the load resistor of a high-frequency ECL delay cell; the element is a controlled MOSFET resistor in parallel with a fixed diffusion resistor.

Abstract: A full swing CMOS output buffer circuit (20,30,40,50) isolates incompatible power supply circuits such as 3.3 v standard and 5 v standard subcircuits, and isolates power supply rails of quiet or powered down buffer circuits from the common external bus. The pullup output transistor (PMOS1) is fabricated in a well (NWELL) of N type carrier semiconductor material formed in a substrate (PSUB) of P type carrier semiconductor material. A P channel NWELL isolation switch transistor (PW1) has a primary current path coupled between the well (NWELL) and high potential power rail (VCC) and a control gate node coupled to the control gate node of the pullup output transistor (PMOS1) for operating substantially in phase. The NWELL isolation switch transistor (PW1) isolates the pullup output transistor (PMOS1) well (NWELL) from the high potential power rail (VCC).

Abstract: An electronic switch to be used in BiCMOS circuitry when CMOS stages are controlled by logic output from (bipolar) TTL stages. Its purpose is to avoid the static leakage current I.sub.cct which can occur in a CMOS stage when the pulldown transistor is turned on while the pullup transistor is not completely turned off. This is a problem which arises when CMOS and TTL stages are coupled; the logic-high output from a TTL stage is sufficient in magnitude to turn on the CMOS pulldown transistor but not to turn off the CMOS pullup transistor. The present invention introduces an ancillary input to the subcircuit encompassing the CMOS input stage and also an ancillary output from one of the CMOS stages of the subcircuit (typically an output buffer) encompassing the TTL output stage. The ancillary output is chosen so as to provide a CMOS logic-high signal whenever the TTL stage is outputting a TTL logic-high signal. The ancillary input is connected to the control node of a switching transistor interposed between V.

Abstract: A lateral PNP transistor structure is fabricated in a BICMOS process utilizing the same steps as are used during the BICMOS process for fabricating NPN and CMOS transistors without requiring additional steps. A base N+ buried layer B/N+BL formed in the IC substrate P/SUB underlies the bipolar PNP transistor. A base Retro NWELL B/NWELL and a base contact Retro NWELL BC/NWELL are formed in the base N+ buried layer B/N+BL using the CMOS Retro NWELL mask, etch and N type introduction sequence. An epitaxial layer EPI of undoped or low doped EPI is deposited across the IC substrate and isolation oxide regions ISOX isolating the PNP transistor are grown during the isolation oxide ISOX mask, etch and grow sequence. The NPN collector sink definition mask, etch and N type introduction sequence is used to form a PNP base contact N+ sink region BC/N+SINK to the BC/NWELL and B/N+BL.