Abstract: A mechanism is provided for biasing placement of a software thread on a currently idle and dispatched processor. The operating system starts with the last logical processor on which the software thread ran and determines whether that processor is idle and dispatched and considers each logical processor until a currently dispatched and idle logical processor is found. If a currently dispatched and idle logical processor is not found, then the operating system biases placing the software thread on an idle logical processor.

Abstract: A solution provided here comprises receiving requests for a service from a plurality of customers, responding to the requests for a service, utilizing a shared infrastructure, and configuring the shared infrastructure, based on stored customer information. Another example of such a solution comprises: analyzing at least one provisioning request; assigning a priority to the provisioning request, based on performance data and stored customer information; configuring a shared infrastructure, according to the provisioning request and the priority; and responding to requests for services, utilizing the shared infrastructure.

Abstract: A wake-and-go mechanism is provided for a data processing system. The wake-and-go mechanism is configured to issue a look-ahead load command on a system bus to read a data value from a target address and perform a comparison operation to determine whether the data value at the target address indicates that an event for which a thread is waiting has occurred. In response to the comparison resulting in a determination that the event has not occurred, the wake-and-go engine populates a wake-and-go storage array with the target address and snooping the target address on the system bus without data exclusivity. In response to the comparison resulting in a determination that the event has occurred, the wake-and-go engine issues a load command on the system bus to read the data value from the target address with data exclusivity.

Abstract: A mechanism is provided for efficient redundancy identification, redundancy removal, and sequential equivalence checking with designs including memory arrays. The mechanism includes an array merging component to optimally merge an array output such that if the address is out-of-bounds or the port is not asserted, the array output is converted to a random output. The mechanism also includes a component for determining the equivalence of enabled array outputs rather than the array outputs directly and creating an enabled array output. The mechanism also includes a component that precludes potentially-redundant array cells from participating in the sequential redundancy removal determination. This component first checks for compatibility of the corresponding arrays, then the corresponding read port enables and addresses, then the corresponding initial values, and finally checking that writes to the corresponding columns yield a compatible set of values.

Abstract: A remote update programming idiom accelerator is configured to detect a complex remote update programming idiom in an instruction sequence of a thread. The complex remote update programming idiom includes a read operation for reading data from a storage location at a remote node, a sequence of instructions for performing an update operation on the data to form result data, and a write operation for writing the result data to the storage location at the remote node. The remote update programming idiom accelerator is configured to determine whether the sequence of instructions is longer than an instruction size threshold and responsive to a determination that the sequence of instructions is not longer than the instruction size threshold, transmit the complex remote update programming idiom to the remote node to perform the update operation on the data at the remote node.

Abstract: A “kill” intrinsic that may be used in programs for designating specific data objects as having been “killed” by a preceding action is provided. The concept of a data object being “killed” is that the compiler is informed that no operations (e.g., loads and stores) on that data object, or its aliases, can be moved across the point in the program flow where the data object is designated as having been “killed.” The “kill” intrinsic limits the reordering capability of an optimization scheduler of a compiler with regard to operations performed on “killed” data objects. The “kill” intrinsic may be used with direct memory access (DMA) operations. Data objects being DMA'ed from a local store of a processor may be “killed” through use of the “kill” intrinsic prior to submitting the DMA request. Data objects being DMA'ed to the local store of the processor may be “killed” after verifying the transfer completes.

Abstract: A mechanism for sharing tasks is provided in which individuals in a share group may signal their intent to complete individual shared tasks and communicate that intent to other individuals in the share group. A required time for completion of the shared tasks may be associated with an individual's signaling of the intent to complete the shared task. The completion of the shared task by the individual signaling intent to complete may be monitored and, if not completed within the associated required time, the performance of the shared task may again he shared with the individuals of the share group. In this way, another individual may signal that individual's intent to perform the shared task and the process may be repeated until the shared task is completed.

Abstract: A mechanism is provided for internally controlling and enhancing advanced test and characterization in a multiple core microprocessor. To decrease the time needed to test a multiple core chip, the mechanism uses micro-architectural support that allows one core, a control core, to run a functional program to test the other cores. Any core on the chip can be designated to be the control core as long as it has already been tested for functionality at one safe frequency and voltage operating point. An external testing device loads a small program into the control core's dedicated memory. The program functionally running on the control core uses micro-architectural support for functional scan and external scan communication to independently test the other cores while adjusting the frequencies and/or voltages of the other cores until failure. The control core may independently test the other cores by starting, stopping, and determining pass/fail results.

Abstract: A metadata file can be automatically generated based on a database instance and a user defined maximum depth. The relationships between data objects that constitute a business object may be visualized in a tree. The maximum depth limits the number of levels in the tree to traverse. A metadata file describes the structure of a business object and relationships between sets of data objects that constitute the business object. The structure defined in the metadata file can be used to export instances of the business object from the database. The exported business object instances can be imported to another database.

Abstract: A computer program product comprises a computer useable medium having a computer readable program for authentication of code, such as boot code. A memory addressing engine is employable to select a portion of a memory, as a function of a step value, as a first input hash value. The step value allows for the non-commutative cumulative hashing of a plurality of memory portions with a second input hash value, such as a previous hash value that has been rotated left. An authenticator circuit is employable to perform a hash upon the portion of memory and the second input hash value. A comparison circuit is then employable to compare an output of the authenticator circuit to an expected value.

Abstract: A mechanism is provided for configuring offline player behavior within a persistent world game. A player agent for an offline player includes an event monitor that monitors for events that occur in a persistent virtual world maintained by a game server. When a game event occurs that triggers an offline player rule, the player agent may generate game events on behalf of the offline player. The player agent may also receive messages from an offline player. The messages may include commands for adding, removing, or editing offline player rules. A message may also include a command to view a list of rules or fire a one-time execution of a rule upon receipt. Therefore, a player may contribute to the persistent virtual world even when offline by sending commands using a messaging client or Web browser.

Abstract: A peer-to-peer file sharing client with background file sharing is provided in a segmented peer-to-peer file sharing network. Each file sharing participant may designate an amount of bandwidth and/or storage space for background file sharing. Peer-to-peer file sharing clients then share file data and content in the background automatically. The client may participate in additional swarms, in the background, to generally increase the number of peers in file sharing networks, thus increasing the speed of downloading desired files for other users.

Abstract: A wake-and-go mechanism is provided for a data processing system. The wake-and-go mechanism is configured to issue a look-ahead load command on a system bus to read a data value from a target address and perform a comparison operation to determine whether the data value at the target address indicates that an event for which a thread is waiting has occurred. In response to the comparison resulting in a determination that the event has not occurred, the wake-and-go engine populates the wake-and-go storage array with the target address and snoops the target address on the system bus.

Abstract: A mechanism is provided for internally controlling and enhancing logic built-in self test in a multiple core microprocessor. The control core may use architectural support for scan and external scan communication (XSCOM) to independently test the other cores while adjusting their frequency and/or voltage. A program loaded onto the control core may adjust the frequency and configure the LBIST to run on each of the cores under test. Once LBIST has completed on a core under test, the control core's program may evaluate the results and decide a next test to run for that core. For isolating failing latch positions, the control core may iteratively configure the LBIST mask and sequence registers on the core under test to determine the location of the failing latch. The control core may control the LBIST stump masks to isolate the failure to a particular latch scan ring and then position within that ring.

Abstract: A mechanism is provided for enforcing accessible content development. The mechanism enforces accessible content development by accessing a tag library descriptor for each of a plurality of markup tags for web content authoring where the tag library descriptor notes one or more tag sub-elements required for accessibility. The mechanism analyzes each markup tag in a piece of web content by comparing the tag library descriptor accessibility requirements to sub-elements included with each markup tag to determine whether all required accessibility sub-elements are present. The mechanism generates an error message if all required accessibility sub-elements of a markup tag are not present.

Abstract: A mechanism is provided for transforming an original database query into a supported database query that can be fully computed by a target database. The original database query comprising a select list including a plurality of expressions, the plurality of expressions having a control break. The plurality of expressions includes an expression that cannot be directly computed by the target database. The mechanism constructs a derived table from the unsupported database query comprising constructing a new select list of the derived table, traversing the plurality of expressions of the select list of the unsupported database query, and adding a GROUP BY expression to the derived table based on the new select list of the derived table. The mechanism constructs the supported database query using the unsupported database query and the derived table.

Abstract: A mechanism is provided for determining whether to use cache affinity as a criterion for software thread dispatching in a shared processor logical partitioning data processing system. The server firmware may store data about when and/or how often logical processors are dispatched. Given these data, the operating system may collect metrics. Using the logical processor metrics, the operating system may determine whether cache affinity is likely to provide a significant performance benefit relative to the cost of dispatching a particular logical processor to the operating system.

Abstract: A single fibre channel switch or serial attached SCSI expander applies zoning on the initiator ports to each of the two ports of one or more drives. The fibre channel switch or serial attached SCSI expander uses zoning to connect both ports of each drive to a single expander and set the zones in the expander such that each zone includes at least one initiator port and one drive port.

Abstract: A mechanism is provided for autonomic component service state management for a multiple function component. The mechanism determines whether independent functions within a multiple function service boundary can be serviced. When a single function experiences a failure that requires service, repair, or replacement, the surviving functions notify the service management software of the state of the independent functions. The service management software then determines the state of the overall component and implements the appropriate service method.

Abstract: A mechanism for in situ verification of capacitive power support is provided. A memory system uses a super capacitor to support a voltage rail when input power is lost or interrupted. The voltage discharge curve is a function of load and capacitance of the component. By stepping the regulated power supply to a lower output within the voltage range and recording voltage and current draw at the super capacitor as it discharges to the new regulator output voltage, the super capacitor holdup capability can be tested.