Abstract: A memory system has mechanisms for scavenging capacity of a super capacitor by removing, or reducing, system load from the super capacitor when the super capacitor voltage decays below a low threshold. The mechanisms then restore the system load to the super capacitor when the super capacitor voltage ramps back above a high threshold. A controller may reduce system load by placing a volatile memory system in a standby state and disabling a field effect transistor to remove power from a non-volatile memory system. A controller may adjust the high threshold and/or a low threshold by setting a digitally controlled potentiometer in a threshold detect circuit via an I2C bus.
Type:
Grant
Filed:
April 8, 2008
Date of Patent:
April 17, 2012
Assignee:
International Business Machines Corporation
Inventors:
Brian J. Cagno, John C. Elliott, Robert A. Kubo, Gregg S. Lucas