Abstract: A method is disclosed for increasing the capacitance of high-density DRAM devices by microlithographic patterning. A semiconductor substrate having a MOS transistor comprising a gate and source/drain regions, and a word line and a bit line is provided. A layer of inter-poly oxide is deposited over the substrate and planarized. Contact holes are etched in the oxide layer until the substrate is exposed. A layer of photoresist is next blanket deposited over the substrate. Using microlithographic methods, the photoresist is then patterned with in-line or staggered micron size features and the underlying inter-poly oxide layer is etched using the photoresist as a mask. The resulting inter-poly oxide surface, therefore, acquires the shape of a micro-folded topography having a roughened surface area of many folds larger than the original flat surface.

Abstract: A method of forming buried contacts in MOSFET and CMOS devices which substantially reduces the depth of the buried contact trench. A split polysilicon process is used to form the gate electrode and contact electrode. The first polysilicon layer is very thin layer of undoped polysilicon, having a thickness of less than 100 Angstroms. The second polysilicon layer is a layer of doped polysilicon having a thickness of between about 950 and 1150 Angstroms. The buried contact can be formed either using ion implantation or diffusion of impurities from the layer of doped second polysilicon into the contact region. When the metal layers are etched to form the gate electrode and contact electrode the resulting buried contact trench is less than 500 Angstroms deep.