Patents Represented by Attorney Steptoe & Johnson LLC
  • Patent number: 7845954
    Abstract: A first circuit board (1) mounted with an electronic component (16) and a second circuit board (2) are vertically connected three-dimensionally through an interconnecting board (3) wherein the terminal portion (6) of the land electrode (5) on the interconnecting board (3) is buried in the termination material (9) of the interconnecting board (3). Consequently, the chance of peeling or cracking due to peeling stress or shearing stress acting between the upper/lower circuit boards and the land electrode by high density mounting, thermal shock or falling impact can be suppressed or buffered resulting in high reliability.
    Type: Grant
    Filed: April 17, 2006
    Date of Patent: December 7, 2010
    Assignee: Panasonic Corporation
    Inventors: Yoshihiro Tomura, Yasushi Nakagiri, Kunio Hibino, Yoshihiko Yagi, Akihiro Miyashita, Masahiro Ono, Masato Mori