Abstract: A double data rate serial encoder is provided. The serial encoder comprises a mux having a plurality of inputs, a plurality of latches coupled to the inputs of the mux, an enabler to enable the latches to update their data inputs, and a counter to select one of the plurality of inputs of the mux for output. In another aspect, the mux provides a glitch-less output during input transitions. The mux includes an output selection algorithm optimized based on a priori knowledge of an input selection sequence provided by the counter.
Type:
Grant
Filed:
November 23, 2005
Date of Patent:
January 1, 2008
Assignee:
Qualcomm Incorporated
Inventors:
George Alan Wiley, Brian Steele, Curtis D. Musfeldt