Abstract: The method is for manufacturing sealed vacuum field emission devices. A field EMITTER TIP is formed on a silicon substrate. A first dielectric layer is formed over the field EMITTER TIP and over the silicon substrate. The first dielectric layer is planarized to provide a smooth top surface co-planar with the top of the field EMITTER TIP. A grid metal layer is formed over the first dielectric layer. A second dielectric layer is formed over the grid metal layer. The second dielectric layer is patterned to provide an opening, vertically located over the field emission device, to the grid metal layer. The grid metal layer is patterned in the area defined by the opening. The first dielectric layer is removed in the region defined by the opening, and also a portion of the first dielectric layer under the grid metal layer. The upper portion of the opening is narrowed.