Abstract: A field-effect semiconductor device, for example a MOSFET of the trench-gate type, comprises side-by-side device cells at a surface (10a) of a semiconductor body (10), and at least one drain connection (41) that extends in a drain trench (40) from the body surface (10a) to an underlying drain region (14a). A channel-accommodating region (15) of the device extends laterally to the drain trench (40). The drain trench (40) extends through the thickness of the channel-accommodating region (15) to the underlying drain region (14a), and the drain connection (41) is separated from the channel-accommodating region (15) by an intermediate insulating layer (24) on side-walls of the drain trench (40). A compact cellular layout can be achieved, with a significant proportion of the total cellular layout area accommodating conduction channels (12). The configuration in a discrete device avoids a need to use a substrate conduction path and so advantageously reduces the ON resistance of the device.

Abstract: A circuit and method for controlling a switch include a level shifter that controls a dynamic, bi-directional high voltage analog switch. The level shifter generally includes transistors, input terminals, a voltage source, a high negative voltage source, and a diode. The configuration of the level shifter, inter alia, allows the switch to be kept ON without a current/signal, prevents dissipation of transistors of the level shifter, and provides constant gate-to-source voltage on the switch transistors for improved linearity.

Abstract: A ladder filter comprises series and shunt resonators (2, 4). The or each shunt resonator (4) has a static capacitance which is more than four times the static capacitance of the input or output series resonators (2i, 2o). This provides increased shunt resonator capacitance which reduces the effective coupling across the a series-shunt section, thereby enabling a smaller number of series-shunt filter sections to used to achieve good stop-band rejection, while still providing good performance in the pass-band. The invention is based on the recognition that filter bandwidth can be traded for improved out-of-band rejection.

Abstract: A power amplifier circuit comprises an amplifying transistor and a dc bias circuit, which comprises an enhanced Wilson current mirror as a self-bias boosting circuit for biasing the amplifying transistor through a bias resistor. The current source and the bias resistor are configured to make the charging rate faster than the discharging rate. Furthermore, the current source of the enhanced Wilson current mirror dictates the quiescent current of the amplifying transistor. Preferably, the quiescent current may be set as in direct proportion to the current source by scaling the emitter area ratios between transistor pairs.

Abstract: The invention relates to a method of manufacturing semiconductor devices in which a slice of semiconductor material is provided with a pn junction aligned parallel to the main surfaces of the slice. After the pn junctions is provided, depressions are provided in one main surface. These depressions cut through the pn junction, thereby dividing the main pn junction into mutually insulated pn junction portions. Before the slice is split up into separate semiconductor bodies, a layer of insulating material is provided. This method of manufacturing semiconductor devices allows for a simple application of the insulating layer to the walls of the depressions.

Abstract: A first device region (20) of one conductivity type is provided adjacent one major surface (11) of a semiconductor body (10). A layer (30) doped with impurities of the opposite conductivity type is provided on the one major surface (11) for forming an extrinsic subsidiary region (41) of a second device region (40) of the opposite conductivity type. An opening (31) is formed through the doped layer (30). Impurities for forming a coupling region (43) of the opposite conductivity type are introduced through the opening (31) prior to defining an insulating first portion (50) on the side wall (32) of the doped layer (30) to form a first window (80). Impurities for forming an intrinsic subsidiary region (42) of the second device region (40) are introduced through the first window (80).