Abstract: Described herein is a reference voltage circuit which includes, in combination, a bit line and first and second word line reference transistors connected to the bit line and operative to be turned on with a reference pulse simultaneously with the turning on of the word lines in the main memory circuit. First and second ferroelectric capacitors are connected to each of the first and second word line reference transistors, respectively, and to a source of plate line switching voltage, and a first precharging transistor is connected between the first ferroelectric capacitor and ground potential. A second precharging transistor is connected between the second ferroelectric capacitor and a further source of switching voltage, so that the first and second ferroelectric capacitors are polarized in a ONE and ZERO state in the manner identical to the logic states of the ferroelectric capacitors in the main ferroelectric memory circuit.