Abstract: A system for synchronizing a wireless receiver is provided. The system includes a first antenna and a second antenna to receive independent wireless signals containing different combination of data packets. The system includes one or more analyzer components operable to determine correlation metrics based on at least a portion of the first received signal and a portion of the second received signal. The system further includes a synchronization component operable to use the correlation metrics to determine a preferred correlation metric for synchronization by the wireless receiver of the first and second received signals to decode the data packet. A method for synchronizing a receiver of two wireless signals is also provided.

Abstract: Systems and methods for providing multiple-input multiple-output (MIMO) detection, comprising a leaf node predictor for receiving a processed communications stream, computing at least one channel metric corresponding to the communications stream for a given channel realization, and generating at least one parameter corresponding to at least one predicted best leaf node candidate for the given channel realization. A MIMO engine receives the at least one parameter and enumerates at least one list of candidate vectors corresponding to the leaf nodes specified by the generated at least one parameter. Some embodiments simulate a MIMO detector over many channel realizations, track channel metric and parameter values used for each channel realization resulting from such simulating, and store, in a look-up table, best values of the tracked values used for a particular channel metric.

Abstract: A packaged semiconductor device includes a semiconductor die including a substrate having a topside including active circuitry and a bottomside with at least one backside metal layer directly attached. A package including a molding material having a die pad and a plurality of leads is encapsulated within the molding material, wherein the leads include an exposed portion that includes a bonding portion. The topside of the semiconductor die is attached to the die pad, and the package includes a gap that exposes the backside metal layer along a bottom surface of the package. Bond wires couple pads on the topside of the semiconductor die to the leads. The bonding portions, the molding material along the bottom surface of the package, and the backside metal layer are all substantially planar to one another.

Abstract: A wirebond-less packaged semiconductor device includes a plurality of I/O contacts, at least one semiconductor die, the semiconductor die having a bottom major surface and a top major surface, the top major surface having at least two electrically isolated electrodes, and a conductive clip system disposed over the top major surface, the clip system comprising at least two electrically isolated sections coupling the electrodes to respective I/O contacts.

Abstract: A pallet (501) supporting a half-etched leadframe with cantilever-type leads (403) without metallic supports during the step of attaching components (510) to the leads in order to assemble an electronic system. After assembly, the pallet is removed before the molding step that encapsulates (601a) the components on the leadframe and mechanically supports (601b) the cantilever leads. The pallet is machined from metal or inert plastic material, tolerates elevated temperatures during soldering, and is reusable for the next assembly batch.

Abstract: A layered message updating method and system for the decoding of LDPC codes with high sub-matrix degree has a scalable foldable and flexible decoder architecture to support LDPC codes with arbitrary high sub-matrix degree with very small hardware overhead and high throughput. Embodiments of the invention support LDPC codes with sub-matrix degree W=>1.

Abstract: Embodiments of the invention provide a system and method to improve the performance of a GNSS receiver using antenna switching. The system has a plurality of antennas and at least one radio frequency RF chain. There are fewer RF chain(s) than antennas. A receiver processes a plurality of signals sent by a plurality of transmitters. The system also includes antenna switches and switch controller. The method includes processing signals from a plurality of satellite vehicles SVs using an antenna selected from a plurality of antennas.

Abstract: A semiconductor device has a chip (101) with gold studs (212) assembled on a tape substrate (102), which has solder balls (103) for attachment to external parts. The tape substrate (about 30 to 70 ?m thick) has on its first surface first copper contact pads (221) covered with a continuous thin nickel layer (222) of about 0.04 to 0.12 ?m thickness. Gold including stud (212) is contacting the nickel. On the second substrate surface are second copper contact pads (231) covered with an alloy layer (about 2 to 3 ?m thick) including gold, copper/tin alloys, and copper/nickel/tin alloys; the alloys are metallurgically attached to the second copper pad and substantially free of unalloyed nickel. A reflow body (103) comprising tin is metallurgically attached to the alloy layer of each second pad.

Abstract: A method of fabricating through silicon via (TSV) die includes depositing a first dielectric layer on a substrate that includes a plurality of TSV die. The TSV die have a topside including active circuitry, a bottomside, and a plurality of TSVs including an inner metal core that reaches from the topside to protruding TSV tips that extend out from the bottomside. The first dielectric layer covers the TSV tips. A portion of the first dielectric layer is removed to expose the TSV tips. At least one metal layer is deposited on the TSV tips to form metal caps on the TSV tips to provide metal capped TSV tips. A second dielectric layer is deposited on the bottomside of the substrate to cover the metal capped TSV tips. A portion of the second dielectric layer is removed to expose a portion of the metal capped TSV tips.

Abstract: In a method for transferring at least one of power and ground signal between a die and a package base of a semiconductor device, a connector is formed there between. The connector, which is disposed above the die attached to the package base, includes a center pad electrically coupled to the die by a plurality of conductive bumps and a finger extending outward from the center pad towards the package base. The finger is electrically coupled to the package base by a conductive pad. A plurality of bond wires are formed to electrically couple the package base and the die. A resistance of a conductive path via the connector is much less than a resistance of a conductive path via any one of the plurality of bond wires to facilitate an efficient transfer of the at least one of power and ground signal.

Abstract: An adaptive transcoder is provided that includes a shared memory containing a plurality of decoder buffers to store incoming data packets, a plurality of decoder instances to control a decoding process to generate image raw data based on the incoming data packets, and a plurality of encoder instances configured to control an encoding process to generate outgoing packets based on the image raw data; and a data processing element containing a plurality of processing cores, and a core controller. Each decoder instance is paired with an encoder instance; and each decoder buffer is associated with a decoder instance. Each decoder buffer includes a monitoring element to monitor a respective decoder buffer, and provide buffer data corresponding to the status of the decoder buffer. Each encoder instance is associated with a processing core; and the core controller uses the buffer data to associate each decoder instance with a processing core.

Abstract: A synchronous Buck converter in a molded package (thickness 101 between 0.8 and 1.0 mm) has vertically assembled control (110) and sync (120) power FET chips and a driver chip (630). The sync chip has one power terminal attached to the leadframe pad (104) and the opposite power terminal covered by a first copper layer (125) connected (210) to a first leadframe terminal (105), the first layer providing a smaller resistance to a current between first terminal and pad than the resistance through the sync chip. The control chip has one power terminal attached to the first layer and the opposite power terminal covered by a second copper layer (115) connected (410) to a second leadframe terminal (106), the second layer providing a smaller resistance to a current from the first to the second terminal than the resistance through the control chip. Connections (210, 410) of layers (125, 115) to leadframe terminals (105, 106) are copper wires of 20 to 50 ?m diameter, enabling currents between 3 and 30 A.

Abstract: A method for forming a packaged electronic device including a package substrate having a top substrate surface including a die attach region including at least one land pad thereon and a first dielectric layer positioned lateral to the land pad and a non-die attach region. A second dielectric layer is formed on the top substrate surface of the package substrate. An IC die which is mounted to the top substrate surface of the package substrate. An underfill layer is formed between the IC die and the die attach region.

Abstract: A through substrate via (TSV) die includes a plurality of TSVs including an outer dielectric sleeve, an inner metal core and protruding TSV tips including sidewalls that emerge from the TSV die. A passivation layer lateral to protruding TSV tips is on a portion of the sidewalls of protruding TSV tips. The passivation layers is absent from a distal portion of protruding TSV tips to provide an exposed portion of the inner metal core. The TSV tips include bulbous distal tip ends which cover a portion of the TSV sidewalls, are over a topmost surface of the outer dielectric sleeve, and have a maximum cross sectional area that is ?25% more as compared to a cross sectional area of the protruding TSV tips below the bulbous distal tip ends.

Abstract: A method for assembling die packages includes attaching contacts on a first side of a plurality of first die to substrate pads on a top surface of a composite carrier. The composite carrier includes a package substrate including at least one embedded metal layer having its bottom surface secured to a semiconductor wafer. The composite carrier minimizes effects of the CTE mismatch between the die and the package substrate during assembly reduces warpage of the die. After the attaching, the semiconductor wafer is removed from the package substrate. Electrically conductive connectors are attached to the bottom surface of the package substrate, and the package substrate is sawed to form a plurality of singulated die packages.

Abstract: A pellet loading apparatus includes a tablet pusher including a support surfaces including a pusher mechanism coupled thereto for vertical movement upon actuation. A tablet holder on the tablet pusher includes locations framed by sidewall members aligned in the vertical direction that form columns having open tops for holding a pellet stacks of mold component pellets. A pellet separator having a solid portion and apertures is sized to fit around a portion of a top mold pellet in the pellet stacks. The pellet separator includes a pellet drive for lateral moving the top mold pellets relative to under pellets so that after lateral movement the top mold pellets are laterally offset from the under pellets. A tablet lifter includes a pellet stopper having receiving positions for receiving top mold pellets upon receipt after a transfer actuation of the pusher mechanism.

Abstract: A method for multiplexing reference signal (RS) transmissions from user equipments (UEs), with the RS having a bandwidth larger than the data signal bandwidth (distributed RS) is provided. A transmission time interval (TTI) comprises of one or more sub-frames and each sub-frame comprises of at least two RS transmission periods and a plurality of data signal transmission periods. A distributed RS is transmitted during at least one of the at least two RS transmission periods in at least one of the sub-frames comprising the TTI. During the remaining RS transmission periods, for a UE having a data signal transmission, the RS bandwidth is substantially the same as the data signal bandwidth (localized RS). The total system bandwidth is divided into contiguous, non-overlapping sub-bandwidths, called reference signal multiplexing blocks (RSMBs). Transmission of distributed RS occurs within an RSMB and does not cross over different RSMBs.

Abstract: An integrated circuit (IC) device includes a substrate having a top surface including substrate pads, and a through substrate via (TSV) die including a semiconductor substrate including a topside semiconductor surface having active circuitry and a bottomside surface. The topside semiconductor surface includes bonding connectors that are coupled to the substrate pads on the top surface of the substrate. A plurality of TSVs include an inner metal core that extends from the topside semiconductor surface to protruding TSV tips which extend out from the bottomside surface. At least one of the plurality of TSVs are dummy TSVs that have their protruding TSV tips exclusive of any electrically connection thereto that provide additional surface area that enhances heat dissipation from the bottomside of the TSV die.

Abstract: Embodiments of the invention provide a method of reacquiring satellite signals quickly. A pseudorange of at least one satellite is estimated. A user's position is also estimated. Then a signal from at one or more satellites may be received. By detecting when the user is stationary, the Doppler frequency estimation can be corrected or the SNR can be boosted more both of which lead to improved performance. The embodiments allow a GNSS receiver to process signals in when the signal level would otherwise be too low—for example indoors. The embodiments can improve performance when one or more satellites are temporarily blocked but one or more satellites are still being tracked.

Abstract: A semiconductor device including a first memory die having a first memory type, a second memory die having a second memory type different from the first memory type, and a logic die such as a microprocessor. The first memory die can be electrically connected to the logic die using a first type of electrical connection preferred for the first memory type. The second memory die can be electrically connected to the logic die using a second type of electrical connection different from the first type of electrical connection which is preferred for the second memory type. Other devices can include dies all of the same type, or two or more dies of a first type and two or more dies of a second type different from the first type.