Abstract: A method and apparatus for causing a data line to be fetched in an order consistent with the data structure of a processor's modified little endian mode or big endian mode of operation is accomplished when the processor requests a particular word that is not currently stored in cache memory. The request includes an address of the particular word and an indication is provided as to whether the processor is operating in the modified little endian mode or the big endian mode. A memory manager, upon receiving the request, retrieves a line of data from memory (storage device) based on the address and the mode of operation. For example, when the big endian mode is used, the line of data is retrieved using a target word first ordering and when the modified little endian mode is used, the line of data is retrieved using a reverse target word first ordering.

Abstract: A system and method for tracing program code within a processor having an embedded cache memory. The non-invasive tracing technique minimizes the need for trace information to be broadcast externally. The tracing technique monitors changes in instruction flow from the normal execution stream of the code. The tracing technique monitors the updating of processor branch target register contents in order to monitor branch target flow of the code. A FIFO and serial logic circuitry is utilized to minimize the number of chip pins required to broadcast the information from the chip. The tracing technique utilizes instruction and data breakpoint debug functions to signal an external trace tool that a trace event has occurred.

Abstract: A method and apparatus for obtaining near 100 percent quiescent current test coverage within a reasonable amount of time is accomplished by providing a plurality of test circuits interdisposed between a plurality of combinational logic circuits. During testing, the testing circuits isolate the input of one combinational logic circuit from the output of the preceding combinational logic, thus allowing the test circuit to stimulate the input of the combinational logic circuit. By performing the input stimulations of the plurality of combinational logic circuits simultaneously, only two test steps are needed to check the quiescent current of the plurality of combinational logic circuits.