Patents Represented by Attorney, Agent or Law Firm Steven Capella, Esq.
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Patent number: 6800503Abstract: A method of fabricating an encapsulated micro electro-mechanical system (MEMS) and making of same that includes forming a dielectric layer, patterning an upper surface of the dielectric layer to form a trench, forming a release material within the trench, patterning an upper surface of the release material to form another trench, forming a first encapsulating layer that includes sidewalls within the another trench, forming a core layer within the first encapsulating layer, and forming a second encapsulating layer above the core layer, where the second encapsulating layer is connected to the sidewalls of the first encapsulating layer. Alternatively, the method includes forming a multilayer MEMS structure by photomasking processes to form a first metal layer, a second layer including a dielectric layer and a second metal layer, and a third metal layer. The core layer and the encapsulating layers are made of materials with complementary electrical, mechanical and/or magnetic properties.Type: GrantFiled: November 20, 2002Date of Patent: October 5, 2004Assignee: International Business Machines CorporationInventors: Joseph T. Kocis, James Tornello, Kevin S. Petrarca, Richard Volant, Seshadri Subbanna
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Patent number: 6696216Abstract: Thiophene-containing photo acid generators having either of the following general formulas: wherein at least one of R1, R2 or R3 is thiophene or thiophene that is substituted with alkyl, alkoxy or cycloalkyl, and the remaining R1, R2 or R3, not containing a thiophene moiety, are independently selected from the group consisting of alkyl, cycloalkyl and aryl, or at least one of R1, R2 or R3 are joined together to form a cyclic moiety having from about 4 to about 8 ring carbon atoms; and Y is a counter ion, are disclosed as well as the use thereof as a component of a chemically amplified resist composition. In addition to the thiophene-containing photo acid generator, the inventive composition includes a chemically amplified base polymer, a solvent, an optional photosensitizer, an optional base, an optional dissolution modifying agent and an optional surfactant.Type: GrantFiled: June 29, 2001Date of Patent: February 24, 2004Assignee: International Business Machines CorporationInventors: Wenjie Li, Pushkara Rao Varanasi, Kuang-Jung Chen
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Patent number: 6667504Abstract: The invention provides a trench storage structure that includes a substrate having a trench, a capacitor conductor in the lower part of the trench, a conductive node strap in the trench adjacent the capacitor conductor, a trench top oxide above the capacitor conductor, and a conductive buried strap in the substrate adjacent the trench top oxide. The trench top oxide includes a doped trench top oxide layer above the conductive strap, and an undoped trench top oxide layer above the doped trench top oxide layer.Type: GrantFiled: March 24, 2003Date of Patent: December 23, 2003Assignees: International Business Machines Corporation, Infineon Technologies North America CorporationInventors: Jochen Beintner, Wolfgang Bergner, Richard A. Conti, Andreas Knorr, Rolf Weis
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Patent number: 6656375Abstract: An anisotropic etching process for a nitride layer of a substrate, the process comprising using an etchant gas which comprises a hydrogen-rich fluorohydrocarbon, an oxidant and a carbon source. The hydrogen-rich fluorohydrocarbon is preferably one of CH3F or CH2F2, the carbon source is preferably one of CO2 or CO, and the oxidant is preferably O2. The fluorohydrocarbon is preferably present in the gas at approximately 7%-35% by volume, the oxidant is preferably present in the gas at approximately 1%-35% by volume, and the carbon source is preferably present in the gas at approximately 30%-92%.Type: GrantFiled: January 28, 1998Date of Patent: December 2, 2003Assignee: International Business Machines CorporationInventors: Michael D. Armacost, David M. Dobuzinsky, John C. Malinowski, Hung Y. Ng, Richard S. Wise, Chienfan Yu
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Patent number: 6555430Abstract: Methods forming a trench region of a trench capacitor structure having increase surface area are provided. One method includes the steps of forming a discontinuous polysilicon layer on exposed walls of a lower trench region, the discontinuous polysilicon layer having gaps therein which expose portions of said substrate; oxidizing the lower trench region such that the exposed portions of said substrate provided by the gaps in the discontinuous polysilicon layer are oxidized into oxide material which forms a smooth and wavy layer with the discontinuous polysilicon layer; and etching said oxide material so as to form smooth hemispherical grooves on the walls of the trench region.Type: GrantFiled: November 28, 2000Date of Patent: April 29, 2003Assignee: International Business Machines CorporationInventors: Michael P. Chudzik, Johnathan Faltermeier, Rajarao Jammy, Stephan Kudelka, Irene McStay, Kenneth T. Settlemyer, Jr., Helmut Horst Tews
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Patent number: 6400128Abstract: A system and method for locating a circuit defect, such as a short or an incipient open, in an electric circuit in a workpiece, such a Printed Circuit Board (PCB) or MultiChip Module (MCM). The circuit is connected to a device for sensitively measuring any resistance change. A thermal stimulus is applied to various subsets of the surface of the workpiece, the thermal stimulus being temporally modulated, and the resistance change measurement correlated with this modulation. By applying well-designed thermal stimulus subsets, resistance measurements may be logically combined which correspond to the plural thermal stimulus subsets. Further, the search region where the defect may be located may be iteratively refined. By measuring the time delay between the thermal stimulus and corresponding resistance change, the depth of a defect below the surface of the workpiece is further determined.Type: GrantFiled: March 19, 2001Date of Patent: June 4, 2002Assignee: International Business Machines CorporationInventors: Daniel Guidotti, Arnold Halperin, Michael E. Scaman, Arthur R. Zingher
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Patent number: 6396096Abstract: A design layout for a memory cell structure is provided that achieves maximized channel length on the active areas, while not constricting the contact area of the capacitor contacts is provided.Type: GrantFiled: June 21, 2000Date of Patent: May 28, 2002Assignees: International Business Machines Corporation, Infineon Technologies North America Corp.Inventors: Young-Jin Park, Carl J. Radens
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Patent number: 6348374Abstract: A method of forming a vertical transistor. A pad layer is formed over a semiconductor substrate. A trough is formed through the pad layer and in the semiconductor substrate. A bit line is formed buried in the trough. The bit line is enclosed by a dielectric material. A strap is formed extending through the dielectric material to connect the bit line to the semiconductor substrate. The trough is filled above the bit line with a conductor. The conductor is cut along its longitudinal axis such that the conductor remains on one side of the trough. Wordline troughs are formed, substantially orthogonal to the bit line, above the semiconductor substrate. A portion of the conductor is removed under the wordline trough to separate the conductor into separate gate conductors. Wordlines are formed in the wordline trough connected to the separate gate conductors.Type: GrantFiled: June 19, 2000Date of Patent: February 19, 2002Assignee: International Business MachinesInventors: Satish D. Athavale, Gary B. Bronner, Ramachandra Divakaruni, Ulrike Gruening, Jack A. Mandelman, Carl J. Radens
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Patent number: 6345399Abstract: The propagation of microfissures from a photoresist to an underlying material layer during lithography and etching can be substantially prevented by placing a hard mask between the photoresist and the material layer to be etched. Specifically, the microfissure propagation is substantially prevented by (a) forming a compressive hard mask on a surface of a non-compressive material layer that is to be patterned by lithography and etching; (b) forming a patterned photoresist on said hard mask, wherein a portion of said hard mask is exposed; (c) removing said exposed portion of said hard mask so as to expose a portion of said non-compressive material layer; and (d) transferring said pattern from said patterned photoresist to said exposed portion of said material layer by etching, wherein said hard mask is selective to said etching and thus substantially prevents the propagation of photoresist microfissures to said material layer.Type: GrantFiled: September 27, 2000Date of Patent: February 12, 2002Assignee: International Business Machines CorporationInventors: Paul C. Jamison, Tina Wagner, Richard S. Wise, Hongwen Yan
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Patent number: 6323127Abstract: A noble metal electrode structure having a cup-like, approximately cylindrical shape, roughened inner and outer surfaces, and a surface area of at least 1 sq. micron or greater is provided as well as a capacitor which includes the noble metal electrode as a bottom electrode. The high-surface area noble metal electrode is formed by electroplating into annular channels that have roughened sidewalls formed by the oxidation of vapor-deposited Si nuclei.Type: GrantFiled: June 22, 2000Date of Patent: November 27, 2001Assignee: International Business Machines CorporationInventors: Panayotis Andricacos, Gregory Costrini, David Edward Kotecki, Katherine Lynn Saenger
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Patent number: 6303263Abstract: The present invention is directed to a high-performance irradiation sensitive resists and to a polymer resin composition useful for making the same. In accordance to the present invention, the polymer resin comprises a dual blocked polymer resins. Specifically, the dual blocked polymer resin comprises at least two different acid labile protecting groups which block some, but not all, of the polar functional groups of the polymer resin. a chemically amplified resist system comprising said dual blocked polymer resin; at least one acid generator; and a solvent is also provided herein.Type: GrantFiled: February 25, 1998Date of Patent: October 16, 2001Assignee: International Business Machines MachinesInventors: Kuang-Jung Chen, Ronald A. DellaGuardia, Wu-Song Huang, Ahmad D. Katnani, Mahmoud M. Khojasteh, Qinghuang Lin
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Patent number: 6297086Abstract: Excimer laser annealing is employed to improve the flexibility of gate activation and source/drain activation as well as to limit the extent of decomposition of a high dielectric constant storage capacitor in fabricating trench storage semiconductor memory devices.Type: GrantFiled: March 11, 1999Date of Patent: October 2, 2001Assignee: International Business Machines CorporationInventors: Suryanarayan G. Hegde, Kam Leung Lee, Jack A. Mandelman, Carl J. Radens
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Patent number: 6288422Abstract: A 6F2 memory cell structure comprising a plurality of capacitors each located in a separate trench in a substrate; a pluralaity of transfer transistors each having a vertical gate dielectric, a gate conductor, and a bitline diffusion, each transistor being located above and electrically connected to a respective trench capacitor; a plurality of troughs in a striped pattern about said transistor, said troughs being spaced apart by a substantially uniform spacing, said plurality of striped troughs comprising a first group of troughs consisting of every other one of said troughs being filled with a dielectric material, and a second group of troughs being the remaining troughs of said plurality, said second group of troughs containing dielectric material, damascened wordlines and damascene wordline contacts; a respective wordline electrical contact connected to each respective gate conductor; and a bitline contacted to each bitline diffusion, wherein said bitline diffusions have a width defined by said spacing ofType: GrantFiled: March 31, 2000Date of Patent: September 11, 2001Assignee: International Business Machines CorporationInventors: Jack A. Mandelman, Rama Divakaruni, Carl Radens
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Patent number: 6281539Abstract: A 6F2 memory cell comprising a plurality of capacitors each located in a separate trench that is formed in a semiconductor substrate; a plurality of transfer transistors each having a vertical gate dielectric, a gate conductor, and a bitline diffusion, each transistor is located above and electrically connected to a respective trench capacitor; a plurality of dielectric-filled isolation trenches in a striped pattern about said transistors, said isolation trenches are spaced apart by a substantially uniform spacing; a respective wordline electrically contacted to each respective gate conductor, said wordline is in the same direction as the isolation stripes; and a bitline in contact with said bitline diffusion, wherein said bitline diffusions have a width that is defined by said spacing of said isolation trenches.Type: GrantFiled: March 31, 2000Date of Patent: August 28, 2001Assignee: International Business Machines CorporationInventors: Jack A. Mandelman, Rama Divakaruni
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Patent number: 6274440Abstract: A structure and method for making a cavity fuse over a gate conductor stack.Type: GrantFiled: March 31, 1999Date of Patent: August 14, 2001Assignee: International Business Machines CorporationInventors: Kenneth C. Arndt, Axel C. Brintzinger, Richard A. Conti, Donna R. Cote, Chandrasekhar Narayan, Ravikumar Ramachandran, Thomas S. Rupp, Senthil K. Srinivasan
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Patent number: 6272054Abstract: A twin cell memory array which includes shielded bitlines is provided. The twin cell memory array includes a plurality of bitlines arranged in one direction in parallel with each other, with every other bitline constituting a bitline pair; a plurality of sense amplifiers being arranged in a line, wherein each sense amplifier is interconnected to two adjacent bitline pairs; a plurality of wordlines arranged in a direction intersecting said plurality of bitlines, wherein a single wordline is coupled to every other bitline; and isolation means located on said plurality of bitlines, said isolation means being arranged such that when every other bitline of said plurality of bitlines is being sensed, the adjacent bitlines of said plurality of bitlines are held at a predetermined potential by a clamping means.Type: GrantFiled: October 31, 2000Date of Patent: August 7, 2001Assignee: International Business Machines CorporationInventors: John E. Barth, Jr., John Atkinson Fifield
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Patent number: 6271080Abstract: A memory cell (8F2 and sub-8F2) formed by: (a) forming a stack of at least four material layers on a surface of a semiconductor substrate, wherein at least two of said material layers of said stack are selectively etchable relative to each other; (b) patternwise etching through said stack to define a critical pattern of remaining stack and spaces where said semiconductor substrate is exposed, said critical pattern defining possible locations for trench capacitors and gate conductors; (c) filling said spaces with a filler material which is selectively etchable relative to a topmost layer of said remaining stack; (d) planarizing the filler material stopping at said topmost layer of said remaining stack; (e) forming trench capacitors in said semiconductor substrate by etching through portions of said filler material and said substrate, wherein said etching removes a portion of said topmost layer of said remaining stack and exposes a portion of a layer of said stack that is next to the topmost layer; (f) planarizType: GrantFiled: December 16, 1999Date of Patent: August 7, 2001Assignee: International Business Machines CorporationInventors: Jack A. Mandelman, Toshiharu Furukawa, William R. Tonti
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Patent number: 6268436Abstract: The present invention is directed to a high-performance irradiation sensitive positive-tone resist and to a method of formulating the same. In one aspect, the polymer resin composition of the present invention comprises a blend of at least two miscible aqueous base soluble polymer resins, wherein one of said aqueous base soluble polymer resins of said blend is partially protected with a high activation energy protecting group and the other aqueous base soluble polymer resin of said blend is partially protected with a low activation energy protecting group. A chemically amplified resist system comprising said polymer resin composition; at least one acid generator; and a solvent is also provided herein.Type: GrantFiled: December 27, 1999Date of Patent: July 31, 2001Assignee: International Business Machines CorporationInventors: Kuang-Jung Chen, Ronald A. DellaGuardia, Wu-Song Huang, Ahmad D. Katnani, Mahmoud M. Khojasteh, Quighuang Lin
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Patent number: 6258732Abstract: An organic dielectric material is patterned on a substrate in a process utilizing a patterned resist which contains a metalloid or metallic element at the time of pattern transfer to the organic dielectric layer. The organic dielectric layer is preferably patterned using an oxygen etching process, most preferably oxygen reactive ion etching. The process advantageously avoids the need for a hard mask.Type: GrantFiled: February 4, 1999Date of Patent: July 10, 2001Assignee: International Business Machines CorporationInventors: Qinghuang Lin, Rebecca D. Mih, Kevin S. Petrarca
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Patent number: 6258689Abstract: Trench capacitors are fabricated utilizing a method which results in a metallic nitride as a portion of a node electrode in a lower region of the trench. The metallic nitride-containing trench electrode exhibits reduced series resistance compared to conventional trench electrodes of similar dimensions, thereby enabling reduced ground rule memory cell layouts and/or reduced cell access time. The trench capacitors of the invention are especially useful as components of DRAM memory cells having various trench configuration and design.Type: GrantFiled: July 26, 2000Date of Patent: July 10, 2001Assignee: International Business Machines CorporationInventors: Gary B. Bronner, Jeffrey P. Gambino, Jack A. Mandelman, Rick L. Mohler, Carl Radens, William R. Tonti