Abstract: A novel voltage selection circuit in which only one of a plurality of voltage levels is selected for application to an output node at any given time. Switching transistors are connected between the output node and associated reference voltages. Switching transistors are controlled by a set of voltage selection signals, each having logical zero and logical one states which are of sufficient magnitude to cause said switching transistors to turn on or turn off, and which are insured to be nonoverlapping. Two of the voltages are ground and VCC, which are switched by associated transistors using voltage selection signals having standard levels, such as ground and VCC. Another voltage VPPP is greater than VCC, and is switched by a switching transistor utilizing a voltage selection signal greater than VCC, preferably equal to VPPP. The wells of the second and third switching transistors are connected in common to VPPP to prevent junction breakdown when VPPP is selected.