Abstract: Novel memory cells utilize source-side injection, allowing very small programming currents. If desired, to-be-programmed cells are programmed simultaneously while not requiring an unacceptably large programming current for any given programming operation. In one embodiment, memory arrays are organized in sectors with each sector being formed of a single column or a group of columns having their control gates connected in common. In one embodiment, a high speed shift register is used in place of a row decoder to serially shift in data for the word lines, with all data for each word line of a sector being contained in the shift register on completion of its serial loading. In one embodiment, speed is improved by utilizing a parallel loaded buffer register which receives parallel data from the high speed shift register and holds that data during the write operation, allowing the shift register to receive serial loaded data during the write operation for use in a subsequent write operation.

Abstract: Container for storing two different substances, having a first compartment containing a liquid, a second compartment containing another liquid, a separating body which separates the two compartments, and a puncturing device comprising a tool which breaks the separating body when required and can be moved by hand by means of at least one transmitting part which transmits compression forces, such that the transmitting part is designed as a puncturing device comprising a press member having a press shank which is lengthened upon appliance of a lateral squeezing force onto the side walls of the compartment containing the puncturing device.

Abstract: In the attachment of surface mounted devices, melting of solder is monitored so that immediately thereafter heating may be stopped. The solder paste, which is stump-grey below the melting point, will radically change its reflectance upon melting, this being detectable by means of a video camera.

Abstract: A novel video server is taught which allows for additional output bandwidth from the server by using multiple physical network interfaces over a single IP subnetwork. This approach is particularly well suited for use with video servers that store and deliver multimedia bit streams by allowing all clients to share the same subnetwork with the server. In this manner, the bandwidth from each of the physical network interface can be combined as needed and assigned as needed in service to any plurality of destinations in the network, allowing all bandwidth to be available for use with one or more clients.

Abstract: A significant reduction in the latency between the time the addressed components of memory are ready and the time addressed data is available to the address components of memory is achieved by processing the raw address information faster than the addition used in the prior art. XOR memory addressing replaces the addition of the base and offset address components with an XOR operation, eliminating carry propagation and reducing overall latency. In another embodiment, a sum-addressed memory (SAM) also eliminates the carry propagation and thus reduce the latency while providing the correct base+offset index to access the memory word line corresponding to the correct addition; thus a SAM causes no XOR duplicate problems.

Abstract: Container for storing two different substances, having a first compartment containing a liquid, a second compartment containing another liquid, a separating body which separates the two compartments, and a tool which breaks the separating body when required and can be moved by hand by means of at least one transmitting part which transmits compression forces, such that the force-transmitting direction of the transmitting part 5 lies at an angle to the direction of movement 6 of the tool 4, and that the transmitting part 5 is rotatably attached by one of its ends to the tool 4 and by its other end to the inside wall 9 of the container.

Abstract: A method for recognizing an object by processing reference feature vectors a collection of reference feature vectors is generated; each representing a reference pattern that belongs to one of a plurality of predefined classes. Each class has associated all reference feature vectors representing reference patterns belonging to that class. For a selected class, an associated hierarchy of one or more sets of possibility regions is generated, wherein for a selected set in the hierarchy the number of possibility regions in said selected set is significantly less than the number of reference feature vectors belonging to said selected class, and such that each reference feature vector belonging to said selected class is contained in at least one possibility region of said selected set, and such that each possibility region of said selected set contains relatively few reference feature vectors not belonging to said selected class.

Abstract: A novel video server is taught which allows for additional output bandwidth from the server by using multiple physical network interfaces over a single IP subnetwork. This approach is particularly well suited for use with video servers that store and deliver multimedia bit streams by allowing all clients to share the same subnetwork with the server. In this manner, the bandwidth from each of the physical network interface can be combined as needed and assigned as needed in service to any plurality of destinations in the network, allowing all bandwidth to be available for use with one or more clients.

Abstract: In accordance with the teachings of this invention, a novel voltage regulator is taught which is capable of being formed solely of MOS devices. This eliminates the need to utilize off chip components to form a stand-alone voltage regulator, and avoid the process complexities and increased cost associated with BICMOS fabrication processes.

Abstract: A novel ATM network provided which includes one or more ATM gateways for interfacing a plurality of T1 or fractional T1 signals with a higher bandwidth ATM network switch. In order to provide high speed and bandwidth utilizing relatively inexpensive and standard components, the data is stored in a memory, such as a video RAM, and pointers are utilized to indicate the type of each piece of data stored in the memory, including its priority for transmission to an ATM switch. In one embodiment of this invention, a plurality of pointer pools are used, each corresponding to a data type having a given priority. Pointers are placed into an appropriate one of the pools to define the order in which data will be transferred to the ATM switch in accordance with the priority of the data type and the receiving bandwidth of its destination in the ATM network. In one embodiment an HDLC controller is used which is suitable for framing a plurality of channels of data received on an incoming data path, such as a T1 channel.

Abstract: A computer data storage device made up of both solid state storage and rotating magnetic disk which maintains a fast response time approaching that of a solid state device for many workloads and improving on the response time of a normal magnetic disk for practically all workloads. The high performance is accomplished by a special hardware configuration coupled with unique procedures and algorithms pertaining to the methodology of placing and maintaining data in the most appropriate media based on actual and projected activity. The system management features a completely searchless method for determining the location of data within and between the two devices. Sufficient solid state memory capacity is incorporated to permit retention of useful, active data, as well as to permit prefetching of data into the solid state component when the probabilities favor such action.

Abstract: A novel dust and debris removal and collection system including a distributed vacuum transport system is provided for connection to a plurality of machines located in one or more shop areas. The central vacuum airflow generation equipment is preferably remotely operated to ensure vacuum generation when a machine is being operated for which dust and debris removal is desired. In order to prevent undesired loss of vacuum, a central valve is used having a outlet port for connection to one or more vacuum sources, and a plurality of inlet ports, each associated with one of a plurality of machines located in the one or more shop areas. The central valve is operated to apply vacuum from the one or more vacuum sources to only that one of the plurality of machines which is in operation, thereby preventing a loss of vacuum to other, non-operating machines.

Abstract: An integrated circuit test apparatus according to an exemplary embodiment includes a first memory section configured to store processor procedures and a second memory section configured to simultaneously store parallel integrated circuit test vectors and serial integrated circuit test vectors. A processor is coupled to the first memory section and to the second memory section. The processor is configured to execute the processor procedures to simultaneously manipulate the parallel integrated circuit test vectors and the serial integrated circuit test vectors located in the second memory to test an integrated circuit. Advantages of the invention include the ability to simultaneously store serial and parallel test vectors and to test a device under test (DUT) with simultaneous serial and parallel test vectors. The combination of serial and parallel test vectors increases performance and efficiency of the test apparatus.

Abstract: A computer data storage device made up of both solid state storage and rotating magnetic disk which maintains a fast response time approaching that of a solid state device for many workloads and improving on the response time of a normal magnetic disk for practically all workloads. The high performance is accomplished by a special hardware configuration coupled with unique procedures and algorithms pertaining to the methodology of placing and maintaining data in the most appropriate media based on actual and projected activity. The system management features a completely searchless method for determining the location of data within and between the two devices. Sufficient solid state memory capacity is incorporated to permit retention of useful, active data, as well as to permit prefetching of data into the solid state component when the probabilities favor such action.

Abstract: A novel process is taught for forming diodes in a process which simultaneously forms MOS or CMOS devices. These diodes have relatively low breakdown voltage, making them suitable for ESD protection devices or as voltage reference diodes. In alternative embodiments, novel low breakdown voltage devices are fabricated in a similar fashion as MOS devices but with doping levels such that the inherent bipolar device has a low breakdown voltage characteristic. In alternative embodiments, novel vertical bipolar transistors are taught, as are SCR devices, having low breakdown voltage characteristics. In one embodiment of this invention, a low breakdown voltage device is integrated directly with a standard MOS transistor, allowing the low breakdown voltage device to trigger the turn on of the standard MOS device, thereby providing large current capacity controlled by the low breakdown voltage device.

Abstract: The invention relates to a thermal desorption device for a gas chromatograph, having a thermostatically controlled oven (1) provided with a carrier gas connection and having an evaporator tube. In this case, the evaporator tube is an interchangeable sample holder tube (5) which can be held by a holding chamber (2) in the oven (1), which sample holder tube can be fitted into a holder piece (6) with one end externally sealed by a seal (8), the holder piece (6) having two seals (9) arranged separated in the region of its casing and being capable of being fitted into a correspondingly designed holder (10), the carrier gas connection (14) opening in the region (12) of an annular gap (13) between the holder (10) and the holder piece (6) between the two seals (9) located on the casing, which annular gap (13) is, for its part, connected to an annular gap (15) surrounding the inserted end of the sample holder tube (5), a trap (18) being connected downstream.

Abstract: A method for operating a cache memory system has a high speed cache memory and a mass storage device operates in a highly efficient manner with a host device. The method operates to dynamically assign segments of the cache memory to correspond to segments of the mass storage device, accept data written by the host into portions of the assigned segments of the cache memory, determines if the elapsed time since any modified data has been written to the cache memory exceeds a predetermined period of time, or if the number of modified segments exceeds a preset limit. If so, the cache memory system enables a transfer mechanism to cause modified data to be written from the cache memory to the mass storage device, based on the location of segments relative to a currently selected track of the mass storage device.

Abstract: The invention relates to an issuing device for disc-shaped parking tickets, which device makes it possible for the parking tickets, provided for issuing, to be presented reliably, on a permanent and requirement-related basis, from a supply, and which is at the same time of a simple design. For this purpose, the issuing device for disc- shaped parking tickets, having a supply container for parking tickets comprises at least one target station for the removal of parking tickets, a transporter which runs between the supply container and the target station and is in the form of a drivable turntable which exhibits receptacles which are distributed over the circumference of the turntable and are intended for temporarily receiving in each case at least one parking ticket which is to be issued from the supply container and for guidance during the transporting movement of the turntable, and further comprises at least one measuring device for identification of the parking ticket which is to be issued in each case.

Abstract: A differential to single ended sense amplifier utilizes a minimum number of stages to convert a differential input signal received from complementary bit lines to a single ended output signal indicative of the state of the data stored in a selected memory cell connected to the complementary bit lines. The circuit is constructed to operate with low voltage swings, thereby increasing the switching speed and thus the sense speed. The sense amplifier includes power down capabilities and the ability to tristate its output terminal while in a standby mode of operation during which it is capable of reading the logic level of an input signal. In one embodiment, the output signal is latched using a simple register when the output stage goes tristated, to continue to provide a valid output signal while a subsequent sense operation is performed.

Abstract: A unique gate array cell and ASIC library development methodology is taught which require no new simulations or new place and route to port a given device design to a same generation process technologies which are available from different vendors. This methodology make use of the minimum design rules from different vendors without reroute of the physical database. This methodology equalizes the functionality and timing characteristics of the macrocell library on a plurality of alternate sources.