Abstract: A ground-plane SOI device including at least a gate region that is formed on a top Si-containing layer of a SOI wafer, said top Si-containing layer being formed on a non-planar buried oxide layer, wherein said non-planar buried oxide layer has a thickness beneath the gate region that is thinner than corresponding oxide layers that are formed in regions not beneath said gate region as well as a method of fabricating the same are provided.
Type:
Grant
Filed:
January 9, 2001
Date of Patent:
December 2, 2003
Assignee:
International Business Machines Corporation
Inventors:
Fariborz Assaderaghi, Tze-chiang Chen, K. Paul Muller, Edward J. Nowak, Devendra K. Sadana, Ghavam G. Shahidi
Abstract: An electronic package and method of making same in which a thermally conductive member is in thermally conductive communication with a semiconductor chip encapsulated within a dielectric material that surrounds portions of a thermally conductive member, semiconductor chip, and a predefined portion of a circuitized substrate. The present invention's thermally conductive member includes two portions of different bending stiffness to assure reduced interfacial stresses between the semiconductor chip and the circuitized substrate.
Type:
Grant
Filed:
October 29, 1999
Date of Patent:
January 14, 2003
Assignee:
International Business Machines Corporation