Abstract: A clock generator system is provided which includes several clock generators each containing a feedback shift register. A parity bit is calculated over the output of all shift registers and compared to an expected value. Additionally, a parity bit is calculated for each shift register, over the bits stored in the shift register, the number of ONE bits in a shift register being constant. A parity error at the output of the shift registers in combination with an error in the additional parity bit allows the correction of the erroneous clock pulse generated by the shift register in error.