Patents Represented by Attorney, Agent or Law Firm Steven J. Phillips
  • Patent number: 6512157
    Abstract: An economical and efficient method for forming a waste containing monolith which meets applicable waste disposal laws, rules and regulations. Removable walls are attached to at least one side of the monolith, thereby forming an interior volume defined by the removable walls and at least one side of the monolith. Waste is placed within the interior volume, whereupon it is submerged in a flowable, curable, monolith forming material (typically concrete) by filling the interior volume with a monolith forming material, and allowing the monolith forming material to cure to a solidified state, thereby forming an expanded monolith integral with the existing monolith. The walls are then removed, thereby leaving the waste encased within said expanded monolith and allowing the removable walls to be reused for further expansion of the monolith.
    Type: Grant
    Filed: December 21, 1999
    Date of Patent: January 28, 2003
    Assignee: AGEC
    Inventors: Steven J. Phillips, Robert G. Alexander, Seleste A. Williams
  • Patent number: 4685631
    Abstract: An apparatus is described for maintaining and delivering a slack reserve length of lead wire between a spool or other source and the wire bonding tool of a lead wire bonding machine. A slack chamber or wind chamber comprised of a housing enclosure, an inlet guide on one side for guiding lead wire into the slack chamber from a spool, an outlet guide on the other side for guiding lead wire out of the slack chamber towards the wire bonding tool maintains the reserve length of lead wire in untangled condition. A source of pressurized dry air or other gas directs a gaseous flow into the slack chamber so that the lead wire is maintained suspended in the gaseous flow in an offset configuration. Wire sensors are operatively positioned in the slack chamber for sensing the offset of lead wire in the wind stream. The wire sensors are coupled to sensor and control logic for controlling the delivery and feeding of lead wire from a spool into the slack chamber.
    Type: Grant
    Filed: February 4, 1985
    Date of Patent: August 11, 1987
    Assignee: Fairchild Semiconductor Corporation
    Inventors: John A. Kurtz, Donald E. Cousens, Mark D. Dufour
  • Patent number: 4680613
    Abstract: A low inductive impedance dual in-line package for an integrated circuit die incorporates a lead frame formed with a central opening without a die attach paddle. A ground plate forms the die attach plane spaced from and parallel with the lead frame. A dielectric layer is formed between the lead frame and ground plate. The lead frame is formed with a ground lead finger electrically coupled in parallel with the ground plate thereby providing a ground path through the ground plate with planar configuration to minimize inductive impedance to ground current and to minimize cross coupling between the electrically active lead fingers of the lead frame. In the preferred embodiment, the lead frame and ground plate are initially supported in a spaced parallel plane relationship by complementary spacing tab elements. During encapsulation, the encapsulation molding compound is introduced between the lead frame and ground plate to form the dielectric layer.
    Type: Grant
    Filed: December 1, 1983
    Date of Patent: July 14, 1987
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Wilbert E. Daniels, Dana J. Fraser
  • Patent number: 4677320
    Abstract: An emitter coupled logic (ECL) to transistor-transistor logic (TTL) translator is provided with a transistor clamp operatively coupled in at least one of the alternate transistor collector paths of the ECL input gate for clamping the voltage applied through the transistor collector path by the ECL current source to a level below saturation of the ECL input gate. The source current generated by the ECL current source may therefore be increased for accelerate turn-off of the TTL output gate of the translator without saturation of the ECL input gate. The transistor clamps are also applied in an ECL to tristate TTL translator in which the TTL output gate is a TTL tristate output device or buffer with dual phase splitter transistors. A dual transistor clamp arrangement in at least one of the ECL input gate transistor collector paths also provides separate clamped base drives to the dual phase splitter transistors for eliminating "current hogging" or base drive preemption.
    Type: Grant
    Filed: May 2, 1985
    Date of Patent: June 30, 1987
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Geoff Hannington