Abstract: To implement a detection technique in which a tumble of and a shock to on articles can be detected even with a simple and low-cost structure. An indicator according to the present invention for detecting a tumble of and a shock to an article moves away from a holding guide in a detector when the detector inclines and goes beyond a limit for inclination. The indicator includes a first part in the shape of rolling on the holding guide when the detector inclines, and a second part smaller than the first part and in the shape of not preventing the first part from rolling. The first part and the second part join together and separate when receiving a shock.

Abstract: A flag and a wait period are used to guarantee that readers of two data values see the updated first value before they see the updated second value, where the second value has to be updated after the first value is updated and thus is dependent on the first value. The first value is updated, and a flag associated with the first data value is set. The flag effectively prevents further updating of the first data value until it has been cleared. A length of time is waited for, such that any reading of the first data value and the second data value is guaranteed to not see the second data value as updated unless the first data value is also seen as updated. The flag is then cleared, such that further updating of the first data value can again occur. The second data value is finally updated.

Abstract: Employing a coherency controller having a primary path and at least one secondary path to at least one interconnection network is disclosed. A method of an embodiment of the invention is performed by the coherency controller of a node. The coherency controller determines whether transactions are being properly sent to other nodes of a plurality of nodes of which the node is a part via a primary path. In response to determining that the transactions are not being properly sent to the at least one interconnection network via the primary path, the coherency controller instead sends the transactions to the other nodes via a secondary path.

Abstract: Content items are revealed to a user based on whether they have been previously reviewed by the user. A number of content items are thus received over time. The content items may be discrete content items, or may be portions of a content stream, and may be received over different media. For each content item, it is determined whether the content item was previously reviewed by a user. Where the content item was not previously reviewed, the item is revealed to the user, such as by being displayed or announced to the user. Where the content item was previously reviewed, the item is hidden from the user, such as by being deleted, by being replaced with an alternative content item, and so on.

Abstract: A data resilience component ensures data integrity by storing a data file and a copy thereof in non-overlapping sectors along the spiral information track of an optical storage medium. The number and location of sectors of the optical storage medium are determined, and, in dependence on this data, the number and location of redundant data bits required to space the stored copy from the stored data file, such that the first sector containing the stored data file and the second sector containing the stored copy are non-adjacent, is determined. The data file, its copy and the redundant bits are then sent in a data stream in their appropriate location to prevent the files from being adjacent for recording.

Abstract: An implementation-efficient, multiple-counter value hardware performance counter is disclosed. A hardware counter of one embodiment includes a memory array and a hardware incrementer. The array stores counter values that are indexable by an index constructed based at least on the number of events to which the counter values correspond. The index may be constructed as a concatenation of a number of bits binarily representing the number of events, and a number of bits binarily representing the number of qualifiers to the events. The incrementer reads the counter values from the array, increments the counter values, and writes the resulting counter values back into the array. The array may be divided into banks over which the counter values are stored, where each bank has a separate instance of the incrementer. Each bank may have a separate instance of the index that indexes only those counters stored in the bank.

Abstract: A flag and a wait period are used to guarantee that readers of two data values see the updated first value before they see the updated second value, where the second value has to be updated after the first value is updated and thus is dependent on the first value. The first value is updated, and a flag associated with the first data value is set. The flag effectively prevents further updating of the first data value until it has been cleared. A length of time is waited for, such that any reading of the first data value and the second data value is guaranteed to not see the second data value as updated unless the first data value is also seen as updated. The flag is then cleared, such that further updating of the first data value can again occur. The second data value is finally updated.

Abstract: Non-inline transaction error correction is disclosed. Where a transaction being processed in a pipeline is determined to include a correctable error, it is output, or drained, from the pipeline into an error queue. The pipeline is switched from a normal mode of operation to a correction mode of operation. In the correction mode, a correction command is inserted into and processed within the pipeline to correct the error within the transaction. The pipeline is switched from the correction mode of operation to a restart mode of operation. In the restart mode, the transaction is reprocessed within the pipeline. The pipeline is then switched from the restart mode of operation back to the normal mode of operation.

Abstract: Read-copy-update (RCU) is performed within real-time and other types of systems, such that memory barrier usage within RCU is reduced. A computerized system includes processors, memory, updaters, and readers. The updaters update contents of a section of the memory by using first and second sets of per-processor counters, first and second sets of per-processor need-memory-barrier bits, and a global flip-counter bit. The global flip-counter bit specifies which of the first or second set of the per-processor counters and the per-processor need-memory-barrier bits is a current set, and which is a last set. The readers read the contents of the section of the memory by using the first and second sets of per-processor counters, the first and second sets of per-processor need-memory-barrier bits, and the global flip-counter bit, in a way that eliminates the need for memory barriers during such read operations.

Abstract: Provided are a method, system, and program for a model publishing framework. An intermediate data structure is generated from a model to include elements providing information on the model, wherein the model defines an object oriented program design. A publisher registry has a plurality of registered publishers. One registered publisher is selected from the publisher registry to use to publish the model. The publisher includes formatting information to generate model output. The selected publisher accesses the intermediate data structure and generates output from the elements in the intermediate data structure according to the formatting information to provide a visualization of the defined model.

Abstract: Service processors within a system are self-clustered. The system can also include an operating system or other software code, a management console, or both. The operating system communicates with the cluster of service processors, where the service processors are self-clustered or otherwise, such as through a memory shared by at least all the service processors. The operating system therefore need not be aware which of the service processors performs a given function. The console communicates with the cluster of service processors, where the service processors are self-clustered or otherwise, through any service processor of the cluster. The console therefore also need not be aware that the service processors have been clustered to perform functionality for the console.

Abstract: Failure recovery within clustered systems is simulated. For each of a number of failure conditions for an initial state of a number of computing elements of a computerized system, a failure state of the computing elements is generated that corresponds to the failure condition and that is based on the initial state of the computing elements. A failure condition may include one or more hardware and/or software failures. For each failure state of the computing elements, a recovery state is then generated, or simulated, for the computing elements, based on the failure state and the initial state of the computing elements and on a number of recovery rules for the computing elements. Each recovery state is then output for subsequent analysis, where such analysis may be either with human interaction, or automatically and without human interaction.

Abstract: Height attributes of features of an object having a plurality of physical features thereon is determined by illuminating the features of the object at a low angle and capturing the reflected light at a camera mounted along the z-axis perpendicular to the object. The reflected light from the features is analyzed to determine if any of the features is of an unacceptable height. The reflected light being either brighter or dimmer than the average determines that the corresponding feature is higher or lower respectively than the average feature.

Abstract: The timing between automatic, non-user-initiated pollings of a server to download data from the server is changed. In one embodiment, user input in relation to polling the server to download data from the server is detected. In response, the timing between automatic, non-user-initiated pollings of the server is changed based at least on the user input detected. In another embodiment, the amount of data downloaded from the server at each polling is tracked. The timing between pollings of the server is thus changed based on the amount of data downloaded from the server during the pollings of the server. The server may be an email server, such that the data downloaded therefrom includes email messages.

Abstract: Tasks are assigned to processors of a system. The resident set size of each task is determined, specifying the amount of physical information allocated thereto, and locational information of this memory with respect to the processors is determined. Each task is assigned one processor, based on the task's resident set size, and the locational information of the task's allocated physical memory. Each task is attempted to be assigned to the processor closest to the largest portion of the physical memory allocated thereto. A number of the tasks may be determined as best suited to run on a given processor, but the given processor may be unable to run them all. The processor may be thus assigned only those tasks that have a greatest amount of physical memory allocated that is closest to the processor, such as the greatest amount or percentage of physical memory allocated that is local to the processor.

Abstract: A system includes one or more transponders, a number of sensors, a tracking sub-system, and a billing sub-system. Each transponder is located in a vehicle capable of being driven on a road having at least a first lane and a second lane in which vehicles move in a same direction. Each sensor is movably located at a point along the road to detect the transponder of each vehicle that has changed between the first and the second lanes at the point. The tracking system is communicatively coupled to the sensors to track when and at which of the points the vehicles have changed between the first and the second lanes. The billing system is to periodically bill users of the vehicles based on when and where the vehicles are driven in the second lane of the road.

Abstract: The temporary storage of a memory line to be stored in a cache while waiting for another memory line to be evicted from the cache is disclosed. A method includes evicting a first memory line currently stored in the cache and storing a second memory line not currently stored in the cache in its place. While the first memory line is being evicted, such as by first being inserted into an eviction queue, the second memory line is temporarily stored in a buffer. The buffer may be a data transfer buffer (DTB). Upon eviction of the first memory line, the second memory line is moved from the buffer into the cache.

Abstract: Utilizing a hardware transactional approach to execute a code section by employing pseudo-transactions, after initially utilizing software locking, is disclosed. A method is disclosed that utilizes a software approach to locking memory to execute a code section relating to memory. The software approach employs a pseudo-transaction to determine whether a hardware approach to transactional memory to execute the threshold would have been successful. Where the hardware approach to transactional memory to execute the code section satisfies a threshold based on success of at least the pseudo-transaction, the method subsequently utilizes the hardware approach to execute the code section. The hardware approach may include starting a transaction inclusive of the code section, conditionally executing the transaction, and, upon successfully completing the transaction, committing execution of the transaction to the memory to which the code section relates.

Abstract: A method and apparatus for a multiprocessor system to simultaneously process multiple data write command issued from one or more peripheral component interface (PCI) devices by controlling and limiting notification of invalidated address information issued by one memory controller managing one group of multiprocessors in a plurality of multiprocessor groups. The method and apparatus permits a multiprocessor system to almost completely process a subsequently issued write command from a PCI device or other type of computer peripheral device before a previous write command has been completely processed by the system. The disclosure is particularly applicable to multiprocessor computer systems which utilize non-uniform memory access (NUMA).

Abstract: A method of queuing of received transactions that have a resource conflict is disclosed. A first node receives a first transaction from a second node, where the first transaction relates to a resource of the first node. The transaction may be a request relating to a memory line of the first node, for instance. It is determined that a second transaction that relates to this resource of the first node is already being processed by the first node. Therefore, the first transaction is enqueued in a conflict queue within the first node. The queuing may be a linked list, a priority queue, or another type of queue. Once the second transaction has been processed, the first transaction is restarted for processing by the first node. The first transaction is then processed by the first node.