Abstract: A warpage preventing substrate is provided. A plurality of first and second conductive traces are respectively formed on a first surface and a second surface of a core layer of the substrate, each conductive trace having a terminal, and a plurality of first and second non-functional traces are respectively formed on the first and second surfaces of the core layer at area free of the conductive traces. The first non-functional traces are arranged in different density from the second non-functional traces in a manner that, stress generated from the first conductive traces and first non-functional traces counteracts stress generated from the second conductive traces and second non-functional traces, to thereby prevent warpage of the substrate and maintain flatness of the substrate.

Abstract: Method and device for the exposure-dependent noise correction in images sensor which can be addressed in lines and columns are converted into digital values and an offset voltage correction is carried out by a summer, a gain correction is carried out by a multiplier, and an exposure-dependent dark current correction is carried out by a further summer. Further, the coefficients that depend on the line number, the column number and the integration time, are determined by linear approximations. As a result, the fixed pattern noise (PFN) in CMOS image sensor can be efficiently suppressed with a relatively low outlay.

Abstract: A digital-to-analog converter arrangement able to process input signals with different signal bandwidth is provided. The arrangement comprises a first input terminal for receiving a first digital input signal, a second input terminal for receiving a second digital input signal and switching means being coupled to the first and second input terminals and being adapted to select between the first and second digital input signals so as to output an intermediate digital signal corresponding to the selected one of the first and second digital input signals. The intermediate digital signal is received by an array of unary digital-to-analog converting elements, each unary digital-to-analog converting element being adapted so that, as an analog output signal, a sum signal of output signals of the unary digital-to-analog converting elements is output.

Abstract: A transformer circuit arrangement has a first transformer (201) with a first lower limit frequency (fu1) and a first upper limit frequency (fo1), and a second transformer (202) with a second lower limit frequency (fu2) and a second upper limit frequency (fo2), whereby the first lower limit frequency (fu1) is smaller than the second upper limit frequency (fu2), and the second upper limit frequency (fo2) is greater than the first upper limit frequency (fo1), the second lower limit frequency (fu2) is preferably not greater or smaller than the first upper limit frequency (fo1) by a factor of 10, at least one input (103, 104) of the first transformer is electrically connected to an input (209, 210) of the second transformer, and at least one output (205, 206) of the first transformer is connected to an output (107, 108) of the second transformer, and the transformer circuit arrangement has a band pass behaviour with a lower overall limit frequency (fuges) and an upper overall limit frequency (foges), whereby the l

Abstract: A module device of stacked semiconductor packages and a method for fabricating the module device are proposed, wherein a first semiconductor package provided, and at least a second semiconductor package is stacked on and electrically connected to the first semiconductor package. The first semiconductor package includes a chip carrier for mounting at least a chip thereon; a circuit board positioned above and electrically connected to the chip carrier by a plurality of conductive elements; and an encapsulant for encapsulating the chip, conductive elements and encapsulant with a top surface of the circuit board being exposed, allowing the second semiconductor package to be electrically connected to the exposed top surface of the circuit board. As the circuit board is incorporated in the first semiconductor package by means of the encapsulant, it provides preferably reliability and workability for electrically connecting the second semiconductor package to the first semiconductor package.

Abstract: A system and a method for a secure trading mechanism combining wireless communication and wired communication are proposed, which, in the condition of two-way trading constructed based on network connection of a wireless communication device functioning in two-way transmission to a trading server and a trading host of a wired communication devices, allow the trading to be performed in real time and the correctness to be determined for data transmitted between different levels of the network according to a secure communication protocol defined in each communication device, so as to assure the security of trading data in transmission, and prevent the trading data from being acquired or changed without authorization.

Abstract: A fabrication method for strengthening flip-chip solder bumps is provided to form a solder bump on a UBM (under bump metallurgy) structure formed over a semiconductor chip, which can prevent the UBM structure against oxidation and contamination and also enhance bondability between the solder bump and UBM structure, thereby improving reliability for packaging the semiconductor chip. This fabrication method is characterized in that before forming the solder bump, a dielectric layer made of BCB (benzo-cyclo-butene) or polyimide is deposited on the UBM structure, and used to protect the UBM structure against oxidation and contamination. Further, before forming the solder bump, a plasma-etching process is performed to remove the dielectric layer; the plasma-etching process is environmental-friendly without having to use a chemical solvent.

Abstract: A cavity-down ball grid array (CDBGA) semiconductor package with a heat spreader is provided, in which a substrate is formed with at least a ground ring, a plurality of ground vias, a ground layer, and at least an opening for receiving at least a chip. The substrate is mounted in a cavity of the heat spreader, and an electrically conductive adhesive is disposed between an inner wall of the cavity and edges of the substrate, so as to allow the ground layer and the ground ring exposed to the edges of the substrate to be electrically connected to the heat spreader by means of the electrically conductive adhesive. By the above arrangement with the heat spreader being included in a grounding circuit path of the chip, ground floatation and excess ground inductance and resistance can be prevented for the semiconductor package, thereby solving heat-dissipation, electromagnetic interference and crosstalk problems.

Abstract: A ball grid array semiconductor packaging technology is provided, which is characterized in that openings of a solder mask are formed on a given edge of a die attachment area, and entire or partial width of each opening is disposed outside the die attachment area. Accordingly, air within the opening of the solder mask is sufficiently eliminated during die bonding process, so as to prevent void formation as adhesive is filled into the opening. Therefore, in the follow-up steps, high temperature in reflowing process will not cause popcorn as in the prior-art, so as to remain good quality of the semiconductor package.

Abstract: Method for fabricating a thermoelectric converter having a plurality of series-connected thermoelement cells, which are connected in series with one another by means of a plurality of first electrical conductor tracks (3) and each of which has a first body (4) made of thermoelectric material of a first conduction type and a second body (5) made of thermoelectric material of a second conduction type. The thermoelement cells are fabricated by means of method steps appertaining to semiconductor technology.

Abstract: An information recording and reproducing device includes a magnetic information detecting section for magnetically detecting magnetic information recorded at a given position on a recording medium, an optical information detecting section for optically detecting optical information recorded at a given position on each track of the recording medium, and a positional control section for controlling a position on the track using the detected magnetic information and optical information.

Abstract: A semiconductor package and a fabricating method thereof are proposed. The semiconductor package includes a semiconductor chip; a plurality of leads surrounding the chip and formed with a plurality of connecting mechanisms and strengthening structures; and an encapsulant for encapsulating the chip and the leads. The foregoing semiconductor package eliminates the use of a die pad, allowing the thickness of the package to be reduced and a surface of the chip to be exposed to the outside of the encapsulant for improving the heat dissipating efficiency thereof. The leads have the same height as the semiconductor package, allowing upper and lower surfaces of the leads to be exposed to the outside of the encapsulant, which further enhance the dissipation of heat generated by the chip in operation.

Abstract: A semiconductor package with a die pad having a recessed portion is proposed, wherein a lead frame is used, having a die pad formed with at least a through hole, and a plurality of leads. A chip is mounted on the die pad and covers the through hole, with a bottom surface of the chip being partly exposed out the through hole. The through hole is formed at its peripheral edge with a recessed portion that dents from a top surface of the die pad and is associated with the through hole. During a molding process, the recessed portion is entirely filled with an encapsulating compound used for encapsulating the chip and die pad. This prevents forming of voids between the chip and die pad, and assures packaged products to be free of die crack or popcorn effect, thereby significantly improving yield and reliability of the packaged products.

Abstract: A lead-frame-based semiconductor package and a fabrication method thereof are proposed. The semiconductor package includes: a lead frame having a plurality of first and second leads, wherein each first lead is formed with an extending portion smaller in thickness than the first lead in a manner that, an upper surface of the extending portion is flush with an upper surface of the first lead, and a lower surface of the extending portion forms a height difference with respect to a lower surface of the first lead; a chip mounted over the upper surfaces of the extending portions, and electrically connected to the leads by bonding wires; an encapsulant for encapsulating the upper surfaces of leads, upper surfaces of extending portions, chip and bonding wires; and a non-conductive material applied over the lower surfaces of extending portions, wherein the lower surfaces of leads are exposed to outside of the non-conductive material.

Abstract: A method of driving a display apparatus including a screen which has pixels arranged in a matrix applies a scanning signal to scanning signal lines connected to the pixels and thus selects each line to scan the screen and also supplies a data signal to those pixels on the selected line via data signal lines, so as to produce a display. Under these conditions, after the screen is scanned twice or more, there is provided a idle period T2 in which all the scanning signal lines are caused to be in a non-scanning state for a period longer than a scanning period T1 in which the screen is scanned once.

Abstract: A method and a device for defining bit allocation table in processing audio signals are provided. The provided method and device can save storage bits and provide light quality as well. In the first step, the total number of bits for storing audio signals is determined. Then the psychoacoustic model provides many signal-to-mask ratios according to the audio signals. At last, the quantizer quantizes the signal-to-mask ratios to generate several quantized levels each of which corresponds to a bit allocation value to define the table of bit allocation. Therefore, fewer or no storage bits are provided for unimportant subbands and signal frames, that is, the efficiency and quality of transmission of audio signals can be raised.

Abstract: For performing double-side printing, an image forming apparatus forms an image on one side of a sheet and then reverses the sheet if the sheet has not been reversed, forms an image on the other side of the sheet and then reverses the sheet if the sheet has been reversed once, and performs idle conveyance in which an image is not formed on a sheet and then discharges the sheet if the sheet has been reversed twice. According to the image forming apparatus and a method of forming an image by this apparatus, procedures of image formation by a user can be prevented from becoming troublesome and the sheets can be discharged in order of the originals.

Abstract: Provided is a semiconductor apparatus manufacturing method capable of severing a base material without producing burrs. A multiplicity of semiconductor apparatuses are produced as follows. A multi-segment base material is obtained by mounting a multiplicity of semiconductor chips on a substrate having a wiring pattern, followed by sealing the semiconductor chips with resin, further followed by attaching a terminal portion having a terminal hole to a back surface of the substrate. A filler is charged in each terminal hole, and, after curing the filler, the base material is severed along a cutting line covering the terminal hole, whereupon the multi-segment base material is divided into separate semiconductor apparatuses. The terminal hole is left exposed along the cut surface of the semiconductor apparatus. Chilled water is applied to the filler filled in the terminal hole to remove it from the terminal hole.

Abstract: A semiconductor device with under bump metallurgy (UBM) and a method for fabricating the semiconductor device are provided, wherein a passivation layer is deposited on a surface of the semiconductor device where a plurality of bond pads are disposed, and formed with a plurality of openings for exposing the bond pads. A first metal layer is deposited over part of each of the bond pads and a portion of the passivation layer around the bond pad; then, a second metal layer is formed over the first metal layer and part of the bond pad uncovered by the first metal layer; subsequently, a third metal layer is formed over the second metal layer to thereby fabricate a UBM structure. Finally, a solder bump is formed on the UBM structure so as to achieve good bondability and electrical connection between the solder bump and UBM structure.