Abstract: A current-limited switch contains a pilot circuit in parallel with a power MOSFET and a reference circuit containing a series of parallel circuits, each of which contains a current mirror MOSFET in parallel with a resistor. A current mirror compensation circuit contains circuitry which shorts out the parallel circuits in sequence as the current through the power MOSFET increases, thereby limiting the size of the current through the power MOSFET. In a preferred embodiment a second MOSFET is used in each parallel circuit in place of the resistor.