Patents Represented by Attorney Steven P. Skabrat
  • Patent number: 6108028
    Abstract: Activation and deactivation of a screen saver in a video conferencing system is based on detected presence of a person in the room wherein the video conferencing system is sited and the current status of a videoconferencing session. The video conferencing system processes a screen save message received from an operating system and informs the operating system not to launch the screen saver if the video conferencing system detects that there is an active video conferencing session or if a presence detection technique has detected a presence in the room or area wherein the video conferencing system is sited within a predetermined time period. When a videoconferencing call is connected or a presence is detected and the screen saver is active, the screen saver is terminated. The presence may be detected by motion, sound, or other techniques.
    Type: Grant
    Filed: November 2, 1998
    Date of Patent: August 22, 2000
    Assignee: Intel Corporation
    Inventors: Rune A. Skarbo, Brian L. Kantor, Christopher C. Lawless, Puneet Kukkal, Wayne R. Hlasnik
  • Patent number: 6088018
    Abstract: Providing input signals to a computer system having a display, the computer system being coupled to a video camera or other video source, is accomplished by capturing video data signals generated by the video camera, the video data signals representing a scene, rendering the scene on the display such that the scene is reflected and transparently visible on the display, analyzing the video data signals to detect an object in the scene, and generating an input signal for the computer system in response to the detected object.
    Type: Grant
    Filed: June 11, 1998
    Date of Patent: July 11, 2000
    Assignee: Intel Corporation
    Inventors: William C. DeLeeuw, Kenneth L. Knowlson, Bradford H. Needham
  • Patent number: 6061092
    Abstract: Elimination of dark fixed pattern noise (DFPN) for tethered CMOS sensor-based digital video cameras is supported by supplying and maintaining a host-based dark image cache. Since the camera is tethered to a host computer system such as a PC, it takes advantage of the storage and processing capabilities of the host to manage the cache. By using a dark image cache for updating of the currently applicable dark image for DFPN cancellation processing, operation of the camera shutter for acquiring dark images is dramatically reduced, thereby using less system resources such as power, and increasing the MTBF of the electromechanical devices such as the camera shutter and associated controls. Dark images are obtained at different integration, gain, and temperature operating characteristics of the camera and stored in the cache. The cached dark images are referenced on the host according to a fixed, predetermined dark column of data in video frames generated by the CMOS sensor image array of the camera.
    Type: Grant
    Filed: December 5, 1997
    Date of Patent: May 9, 2000
    Assignee: Intel Corporation
    Inventors: Ashutosh J. Bakhle, Bradley C. Aldrich
  • Patent number: 6044415
    Abstract: A virtual connection created between an application program and a selected I/O device is used as a communications medium for controlling I/O processing of the I/O device by the application program. The virtual connection is implemented as a system area network connecting a process of the application program and the I/O device. The application program registers the application program's memory that the application program shares with the I/O device (i.e., gives access rights to the I/O device) with the system area network. Once the virtual connection is created and initialized, the application program uses the virtual connection to send request messages for I/O services to the I/O device and to receive reply messages from the I/O device. The I/O device uses the virtual connection to obtain source data from the application program's memory for I/O write operations and to transfer data to the application program's memory for I/O read operations.
    Type: Grant
    Filed: February 27, 1998
    Date of Patent: March 28, 2000
    Assignee: Intel Corporation
    Inventors: William T. Futral, Greg J. Regnier, Stanley S. Amway, III
  • Patent number: 6038598
    Abstract: A content author generates multiple sets of web pages and associated conditions which map to a specified uniform resource locator (URL). The web page sets, associated conditions, and a state information database are installed on a server system. A state setting device, which may be the content author's personal computer, sets the current state of the state information database associated with the web page sets within the server system. Upon receipt of a request for access to a selected web page identified by the URL, the server system evaluates the conditions based on the associated state to determine which one of the web page sets to return in response to a user's request. The state setting device updates the state, thereby dynamically affecting web page set selection, based on factors internal or external to the server system.
    Type: Grant
    Filed: February 23, 1998
    Date of Patent: March 14, 2000
    Assignee: Intel Corporation
    Inventor: Gunner D. Danneels
  • Patent number: 6012227
    Abstract: Tool for obtaining materials out of a cylindrical container includes an elongated handle attached to or integrally formed with a generally pie-shaped end plate. The end plate has a downwardly projecting edge for use as a scraping edge when the tool is rotated within the container. The end plate has an edge in the shape of an arc to conform to the inside radial surface of a cylindrical container during use.
    Type: Grant
    Filed: March 10, 1998
    Date of Patent: January 11, 2000
    Inventor: David C. Lent
  • Patent number: 5991797
    Abstract: A first host system directs an I/O device to transfer data directly between a requesting application program's buffers on a second host system and an I/O unit coupled to the I/O device without the need to pass through the first host system. Since the first host system retains control of the I/O request, it maintains security and protection features at the same time as realizing increases in performance gained from not having to participate in the actual data transfer. This direct movement capability supports peer-to-peer operation where a number of different I/O units, each with its own physical memory addressing domain, require access to the same I/O device. The direct movement capability is also useful in clustered systems. Clustered host systems are allowed direct access to an I/O device for data transfer without intervention by the host system owning the I/O device.
    Type: Grant
    Filed: December 23, 1997
    Date of Patent: November 23, 1999
    Assignee: Intel Corporation
    Inventors: William T. Futral, Greg J. Regnier
  • Patent number: 5991399
    Abstract: Secure distribution of a private key to a user's application program (also called a "trusted player" such as a DVD player or CD-ROM player) with conditional access based on verification of the trusted player's integrity and authenticity is provided. Once validated, the trusted player uses the private key to decrypt encrypted digital content. The private key is dynamically generated, associated with specific digital content, and communicated in real-time from a server to the trusted player in a secure manner, thereby controlling access to encrypted digital content. The key is wrapped into an executable tamper resistant key module in which the key can only be used by the right trusted player as determined by the server based on user requests and payment. The key module plugs in to the trusted player and executes to validate the player and decrypt the content.
    Type: Grant
    Filed: December 18, 1997
    Date of Patent: November 23, 1999
    Assignee: Intel Corporation
    Inventors: Gary L. Graunke, John Carbajal, Richard L. Maliszewski, Carlos V. Rozas
  • Patent number: 5974550
    Abstract: Authenticating a remote process operating in an address space different than that of a local process includes the steps of creating, by the local process, a tamper resistant module containing a temporary secret, sending the tamper resistant module and a challenge from the local process to the remote process, executing the tamper resistant module by the remote process and recovering the secret when the integrity of the remote process is verified by the tamper resistant module, encoding the challenge using the secret to produce a response, sending the response to the local process, and decoding the response by the local process. Optionally, the tamper resistant module includes a request for information from the second process and the response includes the answer to the request for information.
    Type: Grant
    Filed: December 12, 1997
    Date of Patent: October 26, 1999
    Assignee: Intel Corporation
    Inventor: Richard L. Maliszewski
  • Patent number: 5963371
    Abstract: Displaying data private to a first user and data private to a second, collocated user on a single computer display is achieved by providing two pairs of stereoscopic glasses, one for each user, and modifying the glasses by swapping one of the lens from the first pair with one of the lens of the second pair so that the modified first pair of glasses allows viewing of the display in a first state and the modified second pair of glasses allows viewing of the display in a second state. The data private to the first user is displayed when the display is in the first state and the data private to the second user is displayed when the display is in the second state. The display is alternately switched between the first and second states many times per second, thereby providing private displays for each user. In one embodiment, the stereoscopic glasses are polarized glasses and the display includes a polarizing filter. In another embodiment, the stereoscopic glasses are shutter glasses.
    Type: Grant
    Filed: February 4, 1998
    Date of Patent: October 5, 1999
    Assignee: Intel Corporation
    Inventors: Bradford H Needham, David H Koizumi
  • Patent number: 5660110
    Abstract: A plate mounter for mounting flexible printing plates on a printing cylinder used in flexographic and letterpress printing processes includes a frame and a table top having a top flat surface located above the frame for supporting the printing plate. The table top is horizontally slidable on lineal bearings towards and away from an operator of the plate mounter. Two opposing vertical support members are joined by a stabilizing bar with an attached handle. The vertical support members are attached to the frame such that they may be moved radially at the bottom end. In between the vertical support members are a plurality of carriage rods holding a horizontal adjustable cylinder carriage. The carriage slides to the left and right along the rods. Attached to the carriage is a tapered spindle facing the right vertical support member. A matching tapered spindle attaches to the right vertical support member. The spindles hold the printing cylinder.
    Type: Grant
    Filed: February 22, 1996
    Date of Patent: August 26, 1997
    Assignee: Trinity Products, Inc.
    Inventor: Bruce J. Klang
  • Patent number: 5570397
    Abstract: A redundant clock signal generator which allows the use of differing quantities of oscillators, depending on the degree of reliability desired. Synchronizers accompany each oscillator, and phase detectors monitor the phase deviation between any two oscillators in which synchronization is desired. Multiple pairs of oscillators are synchronized to produce a group of simultaneously synchronized clock signals, which are all concurrently available. Selection circuitry selects a predetermined number of the synchronized clock signals at the request of the selection control circuitry. The selection control circuitry determines which of the synchronized clock signals are to be selected either automatically or through manual intervention. Automatic selection can be triggered upon notification to the selection control circuitry of an error condition.
    Type: Grant
    Filed: December 23, 1993
    Date of Patent: October 29, 1996
    Assignee: Unisys Corporation
    Inventor: Thomas T. Kubista
  • Patent number: 5539888
    Abstract: A method and apparatus for executing conditional branch instructions by a data processing system containing a programmable microprocessor and multiple VLSI gate arrays connected by a bi-directional bus, whereby a branch condition is obtained from a storage location resident on a VLSI gate array executing asynchronous and external to the microprocessor. The branch condition is fetched and evaluated in parallel with the fetching of the branch target address and the incrementing of the program counter. The microprocessor changes instruction sequence control depending on the results of the branch condition evaluation.
    Type: Grant
    Filed: January 6, 1995
    Date of Patent: July 23, 1996
    Assignee: UNISYS Corporation
    Inventors: Larry L. Byers, Joseba M. De Subijana, Wayne A. Michaelson
  • Patent number: 5535405
    Abstract: A microsequencer bus controller system provides a flexible and efficient mechanism for controlling multiple gate arrays called stations embedded within a larger computer system. A control store memory, loaded at system initialization time, holds fixed-length instructions simultaneously executed by dual reduced instruction set (RISC) microprocessors which interface with the multiple stations over a bi-directional bus. The master microprocessor compares the result of the processing of each instruction with the slave microprocessor's result to detect any differences, thereby minimizing error latency. Master and slave microprocessors each control half of the stations on the bus. Data widths of 32-bit and 36-bit words are supported by the microprocessors, bus, and stations.
    Type: Grant
    Filed: December 23, 1993
    Date of Patent: July 9, 1996
    Assignee: UNISYS Corporation
    Inventors: Larry L. Byers, Joseba M. De Subijana, Wayne A. Michaelson
  • Patent number: 5524218
    Abstract: A system for communicating data between a main processor and a peripheral processor over a fiber optic interface. The interface is a dedicated, point-to-point link operating in full-duplex, asynchronous mode. Dual fibers and physical layer controllers are used in a cascaded fashion to double the throughput of the interface. Frame control logic coordinates formatting of data into frames for transmission over the interface. Frame format and interface protocol are based on FDDI, but are improved to more efficiently transfer data in a point-to-point implementation. Frame Check Sequences are generated and verified to ensure error-free data transfers. Frame sending and frame receiving logic communicate with the main and peripheral processors, accepting data transfer requests and forwarding received data.
    Type: Grant
    Filed: December 23, 1993
    Date of Patent: June 4, 1996
    Assignee: Unisys Corporation
    Inventors: Larry L. Byers, Donald M. Davies, Joseba M. Desubijana, Michael E. Mayer, Randall L. Piper, Lloyd E. Thorsbakken, Steven M. Wierdsma
  • Patent number: 5519876
    Abstract: A bus architecture includes address lines, data lines, and control signals to allow a processor to communicate with a VLSI gate array. The address lines are interpreted by the VLSI gate array to select either multi-bit registers or single bit designators resident on the VLSI gate array depending on which control signal is received from the processor. Dual address decode logic on the VLSI gate array senses control signals indicating a request to read from a register, write to a register, and set, clear, or test a designator, and decodes the address received to select the appropriate storage location for the requested function.
    Type: Grant
    Filed: December 23, 1993
    Date of Patent: May 21, 1996
    Assignee: UNISYS Corporation
    Inventors: Larry L. Byers, Joseba M. De Subijana, Wayne A. Michaelson
  • Patent number: 5515507
    Abstract: A bus architecture and associated circuitry for providing communication between processors and multiple gate arrays whereby the size of the data being transferred may be either full words of 32-bits or 36-bits per word, or half words of 16-bits or 18-bits per word. Parity generation logic operates on the data to be sent over the bus to generate a parity value from the correct data bits depending on the selected data word size. Parity checking logic operates on the data received from the bus to check the parity of the correct data bits depending on the selected data word size.
    Type: Grant
    Filed: December 23, 1993
    Date of Patent: May 7, 1996
    Assignee: Unisys Corporation
    Inventors: Larry L. Byers, Joseba M. De Subijana, Wayne A. Michaelson, Lloyd E. Thorsbakken, Howard H. Tran
  • Patent number: 5495598
    Abstract: A method and apparatus for detecting stuck faults in a signal line used to communicate a branch condition for executing conditional branch instructions by a data processing system containing a programmable microprocessor and multiple VLSI gate arrays connected by a bi-directional bus, whereby the branch condition is obtained from a storage location resident on a VLSI gate array executing asynchronous and external to the microprocessor. The branch condition is fetched and evaluated in parallel with the fetching of the branch target address and the incrementing of the program counter. The microprocessor changes instruction sequence control depending on the results of the branch condition evaluation.
    Type: Grant
    Filed: December 23, 1993
    Date of Patent: February 27, 1996
    Assignee: Unisys Corporation
    Inventors: Larry L. Byers, Joseba M. De Subijana, Wayne A. Michaelson
  • Patent number: 5493676
    Abstract: An apparatus which includes one or more optical disk memory systems, one or more magnetic disk memory systems, and one semiconductor memory system, to store large amounts of data while operating under potentially severe environmental conditions. The preferred storage media for the apparatus is the optical disk memory system, but when environmental conditions do not permit successful operation of the optical disk memory, the apparatus switches storage of data to an alternate storage media such as magnetic disk memory or semiconductor memory until the severe environmental conditions subside. When environmental conditions subside, the optical disk memory is updated with the data stored on magnetic disk memory and semiconductor memory. Monitoring of environmental conditions is performed by the storage media systems, not by environmental sensors external to the system.
    Type: Grant
    Filed: February 6, 1995
    Date of Patent: February 20, 1996
    Assignee: Unisys Corporation
    Inventor: Dennis L. Amundson
  • Patent number: 5487159
    Abstract: A method and system for executing shift, mask, and merge operations on two operands specified by one instruction contains two registers holding operand data and separate shift, mask, and merge logic. A programmer-defined set of mask and merge indicators controls the mask and merge operations. Each mask and merge indicator is represented as a single bit but controls a pair of bits in an operand. If the first operand is selected by the programmer, it is shifted and then masked. The result of the shift and mask operations is merged with the second operand. If the second operand is selected, it is shifted and masked, and the result is merged with the first operand. Final results are stored for processing by subsequent instructions.
    Type: Grant
    Filed: December 23, 1993
    Date of Patent: January 23, 1996
    Assignee: Unisys Corporation
    Inventors: Larry L. Byers, Joseba M. De Subijana, Wayne A. Michaelson