Abstract: In one embodiment, a print bar includes: a substrate having a longer part and a shorter part extending along and parallel to the longer part such that each end of the longer part extends past each end of the shorter part; and multiple printhead dies on the longer part of the substrate. In another embodiment, a modular print bar includes a first module including multiple printhead dies joined together end to end and a second module including multiple printhead dies joined together end to end. The second module is lapped together end to end with the first module.

Abstract: An improved storage node junction between a doped active area in a semiconductor substrate and an overlying layer of polysilicon, such as the storage node junction in a DRAM memory cell. The area and perimeter of the storage node junction is significantly reduced and the junction is moved away from the adjacent isolation structure. An exemplary semiconductor device incorporating the new junction includes a storage node junction between a conductive polysilicon layer and an active area on a semiconductor substrate, the substrate having been subjected to LOCOS steps to create active areas bounded by a region of field oxide. An insulated gate electrode is formed over an active area on the substrate, which has been doped to a first conductivity type. A contact region comprising a portion of the active area extends laterally between one side of the gate electrode and the field oxide region.

Abstract: An isolation structure providing electrical isolation in two dimensions between memory cells in semiconductor memory devices. The isolation structure comprises a trench formed in a substrate of a semiconductor memory device such as a Dynamic Random Access Memory (DRAM). The trench is lined with an insulating material and filled with polysilicon to form a floating gate. An electrical charge is then injected into the polysilicon floating gate. The isolation structure is located between memory cells in an array to provide isolation between cells in sub-micron spacing by combining the characteristics of trench and field isolation. The electrical charge is injected into the polysilicon floating gate by applying a charging voltage to the wordlines of the memory cell array. The charging voltage is applied periodically as necessary to maintain effective isolation. Two dimensional isolation is achieved by extending the trench to surround each pair of memory cells sharing a common bitline contact.

Abstract: A method for removing contaminants from a semiconductor wafer having a spin on coating of material. Contaminants are removed by applying a cleaning solution to the periphery, and preferably, the exposed backside of the wafer after the edge bead has been dissolved and removed. The cleaning solution is formulated to react chemically with unwanted coating material residue to form a compound that may be ejected from the periphery of the spinning wafer. Any residual solution or precipitate that is not ejected from the wafer may be rinsed away with water, preferably deionized water. One exemplary use of this method is the removal of metallic contaminants that may be left on the periphery and backside of a wafer after the formation of ferroelectric film coatings. A cleaning solution comprising a mixture of hydrochloric acid HCl and water H.sub.2 O or ammonium hydroxide NH.sub.4 OH and water H.sub.2 O is applied to the periphery of the spinning wafer.

Abstract: A process for forming vertical contacts in the manufacture of integrated circuits, and devices so manufactured. The process eliminates the need for precise mask alignment and allows the etch of the contact hole to be controlled independent of the etch of the interconnect trough. The process includes the steps of: forming an insulating layer on the surface of a substrate; forming an etch stop layer on the surface of the insulating layer; forming an opening in the etch stop layer; etching to a first depth through the opening in the etch stop layer and into the insulating layer to form an interconnect trough; forming a photoresist mask on the surface of the etch stop layer and in the trough; and continuing to etch through the insulating layer until reaching the surface of the substrate to form a contact hole. The above process may be repeated one or more times during the formation of multi-level metal integrated circuits.

Abstract: An apparatus and method for downloading firmware upgrades to a targeted remote field configurable embedded computer system over a computer network. The targeted device need not be disconnected from the network and requires no human intervention at the remote site. The entire firmware, including the downloading mechanism, can be updated in an efficient manner.

Abstract: A remote control system for remotely controlling a Microsoft Windows or other GUI-based first computer from a second computer over the internet using only a standard world-wide-web hypertext browser on the second computer. The second controlling computer may be dissimilar from the first controlled computer user interface, underlying operating system, and hardware architecture.

Abstract: A clamping device having a front member, a back member opposing the front member, a pair of opposing side members, a stop block and a clamping mechanism. The side members extend between and connect the front member and the back member. The work piece is supported by and between the side members. The stop block is interposed between the back member and the work piece. The clamping mechanism, which is operatively coupled between the front member and the work piece, exerts a clamping force against the work piece to press the work piece against the stop block. In this way, the work piece is clamped between the front member and the back member.

Abstract: A floating memory device utilizing a composite oxide/oxynitride or oxide/oxynitride/oxide interpoly dielectric.

Abstract: An etch process that uses a single partially etched spacer insulating layer to form both sidewall spacers and a diffusion barrier that protect areas of the substrate during subsequent processing steps in the formation of semiconductor devices such as Dynamic Random Access Memories (DRAMs). The process includes the steps of: (a) forming a gate electrode over a semiconductor substrate; (b) defining first and second contact regions in the substrate adjacent sides of the gate electrode; (c) conformally depositing a spacer insulating layer over the gate electrode and the contact regions; and (d) partially etching the spacer insulating layer to remove only a portion of the thickness of the spacer insulating layer at least over the contact regions of the substrate.

Abstract: Straw bales are used in conjunction with a skeletal framework to form various structurally stable building components such as walls and floors. Straw bales and horizontal trussing members are combined to form a truss. The truss has of a pair of trussing members operatively connected to one or more bales. The trussing members, which are positioned opposite one another along the edges of the bale, form the chords of the truss. The bales form the web of the truss. The trussing members are one of the basic components of the skeletal framework used to construct the various composite structures embodying the invention. In the composite structures, straw bales are arranged in layers within a skeletal framework. The skeletal framework includes the trussing members and a series of rods positioned along the center line of the layered bales. The trussing members in each pair are positioned opposite one another along the edges of the bales at the interfaces between the layers of bales.

Abstract: A new and improved static random access memory (SRAM) cell wherein separate regions of polysilicon are formed over a silicon substrate and are separated by defined openings therein into which oxide filler material is introduced to render the regions of polysilicon and oxide substantially co-planar at their upper surfaces. An access transistor and a thin film load transistor are formed within and adjacent to first and second regions of the polysilicon, respectively, and yet a third, pull down transistor is formed within and adjacent to a third polysilicon region. The thin film transistor includes a thin second layer of polysilicon which is electrically isolated from the second one of the polysilicon regions and is doped to form therein source, drain and channel regions. Advantageously, the thin film transistor is formed on this substantially planar surface, thereby improving process yields and device performance.

Abstract: Various embodiments of a reclosable pouch device and methods for using the device in surgery are shown and described. The reclosable pouch has a wand and a rod attached to the wand near the front and extending back generally parallel to the wand. A part of the rod is flexible for bowing out from the wand when the rod handle is pushed forward and for straightening to come close to the wand when the rod handle is pulled backward. The handle is a part of the rod near the back, which may be rigid, rigid and slidably connected to the wand, or flexible and slidably connected to the wand. A bag may be attached to the rod and wand for receiving a mass during surgery. When the rod bows out, the bag is opened. When the rod straightens, the bag is closed to form a seal. A preferred embodiment includes a slot system having a channel with the rod received in the channel, held in the channel for part of its length, and capable of bowing out of the channel for part of its length.

Abstract: A tool for holding electrical boxes in position for attachment to upright studs in residential and commercial building construction. The tool comprises a main body made of an elongated tubular support member, a holder attached to the main body for releasably holding an electrical box in position for installation, a height adjuster connected to the main body for positioning the electrical box at a predetermined distance above the floor, a depth adjuster attached to the main body for positioning the electrical box at a predetermined depth relative to the face of the upright stud, and an alignment device attached to the main body for positioning the electrical box so that the sides of the box are parallel to the sides of the upright stud. One aspect of the invention provides a clamping trigger for automatic activation of the box gripping force. The clamping trigger is located and configured so that electrical boxes which are presented in misalignment do not activate the trigger.