Abstract: In one method according to the present invention, an integrated circuit chip is fabricated by the following steps:1) providing a trial layout in the chip for a victim net and a set of aggressor nets which have segments that lie next to the victim net;2) assigning to the trial layout of the victim net, the parameters of--a line capacitance, a line resistance, and a driver output resistance; and assigning to the trial layout of each aggressor net, the parameters of--a coupling capacitance to the victim net, and a voltage transition;3) estimating, for each aggressor net, a respective peak crosstalk voltage V.sub.p which the aggressor net couples into the victim net as a function V.sub.p =K(e.sup.-X -e.sup.

Abstract: A memory in an integrated circuit chip includes an array of memory cells and a read/write circuit which performs precharge and sense operations on the array for a time interval that is set by the width of a pulse signal. This pulse signal is generated by a pulse generator circuit which contains transistors that switch on and off at an unpredictable speed; and consequently, the width of the pulse signal has a large tolerance. To decrease this large tolerance in the pulse signal, a compensation circuit is provided which includes a plurality of compensation components for the pulse generator. This compensation circuit selectively couples the compensation components to the pulse generator such that the selectively coupled components in combination with the pulse generator's transistors produce the pulse signal with a precise width that has an insignificant tolerance.

Abstract: A multipoint-to-point CDMA communication system comprises a plurality of CDMA transmitting stations and a single CDMA receiving station, all of which are intercoupled to each other over one CDMA channel and one feedback channel. On the one CDMA channel, the plurality of CDMA transmitting stations simultaneously send respective CDMA signals to the receiving station. In the receiving station, respective time differences are measured between a reference clock signal and the spreading codes in the CDMA signals from each of the CDMA transmitting stations; and these time differences are indicated in respective error signals which the CDMA receiving station sends on the feedback channel to each of the CDMA transmitting stations. Each CDMA station responds to its error signals by time shifting its spreading code such that it arrives in the receiving station in synchronization with the reference clock signal.

Abstract: A dual frequency waveguide switch passes electromagnetic waves in the X-band along one route, and passes electromagnetic waves in the Ku-band along a different route. This switch includes a housing which has first, second, and third openings for the electromagnetic waves to pass through; and a movable member, mounted in the housing, having first and second passageways. The first passageway is shaped to pass electromagnetic waves in both the X-band and the Ku-band, and the second passageway is shaped to pass electromagnetic waves in the Ku-band but reject electromagnetic waves in the X-band. A forcing mechanism forces the moveable member to a position "A" in the housing where the first passageway interconnects the first opening to the second opening, and to a position "B" where the second passageway interconnects the first opening to the third opening.

Abstract: Multiple numbers of "sets" of sender-receiver units operate concurrently to transfer blocks of data. The number of blocks to be transferred in each set is predetermined by a main host computer which registers the number-of-blocks-to-be-transferred into a protocol-controller in each set of sender-receiver units. An associated data feeder control system monitors the number of data blocks residing in a buffer memory, which has dedicated storage for each sender-receiver unit, and will only permit data block transfer to receiver units only to the amount presently available in the buffer memory until, eventually, the predetermined number of data blocks, for each set, is transferred to completion.

Abstract: The method of the present invention is useful in a computer system having a user interface, a memory, a repository and a database. The method is a repository program executed by the computer system for maintaining a history of objects stored in the repository. The method comprises the steps of determining if the object is a new logical object, and if so constructing a new versioned object; and, if not retrieving from the repository an object on which a new state is to be based. If the new state is being derived from only one object, then reserving the object. If the state is being derived from two objects, then retrieving from the repository the other object on which the new state is based, and merging the two objects. If the state changes are to be retained, then replacing the object; and, if the state changes are not to be retained, then unreserving the object.

Abstract: An electromechanical module comprises an IC package having a top surface which dissipates heat and a heat sink which is held by a frame in direct thermal contact with the top surface. This frame includes a pair of spaced-apart elongated beams and a pair of end members which connect to opposite ends of the beams; and the beams together with the end members surround the IC package and expose all of the top surface. Thus, the heat sink can be in direct thermal contact with all of the top surface and can extend past it without having to step up to get over the frame. To attach/remove the frame from the IC package, each end member has at least one leg with a lip that catches on the bottom surface of the IC package; and, when the beams are manually bowed, the lips on the legs move further apart and past the bottom surface.

Abstract: A diagnostic protocol and display system wherein the cable bus output of a computer to a printer is sensed to select coded error data out of the output stream in order to activate a visual display of coded error data for benefit of the human operator.

Abstract: A plurality of digital modules on a Futurebus Plus common system bus means in a network are connected by the Futurebus Plus system bus for transfer of data between modules. A sending module (master) transmits address and message data on the bus to a receiving module (slave). Each module provides an interface having a Longitudinal Redundancy Checker such that the sending module transmits a first check word to the receiving module which generates a second check-word. If these check words match, then the data is accepted as good. Thus, the network can work continuously using the system bus even while new digital modules are inserted onto the system bus or detached from the system bus.

Abstract: A multi-cache memory system resides on-chip with a system interface to external memory. A general cache memory holds frequently used data and OPCODES for delivery to a processor in one clock cycle. A microcode cache holds frequently used microcode instruction words for delivery to the processor in one clock cycle. Both general and microcode cache memories operate to replace less frequently used OPCODES, data words, and microcode instruction words, with more frequently used words.

Abstract: A heat transfer module, comprises: a heat generating unit and a heat receiving unit which are separated by a gap; a compliant body, having microscopic voids therethrough, which is compressed into the gap; and a liquid metal alloy that is absorbed in the microscopic voids in the compliant body. Further, the heat transfer module also includes a seal ring in the gap which surrounds the compliant body and which is spaced apart from the compliant body; and, the compliant body is intentionally compressed so much that a portion of the liquid metal alloy is squeezed from the compliant body into the space between the compliant body and the seal ring. Squeezing liquid metal alloy from the compliant body lowers the thermal resistance between the heat generating unit and the heat receiving unit by increasing the area through which heat is transferred and by increasing the thermal conductivity through the compliant body.

Abstract: A system for equal utilization of blocks of flash memory whereby a processor using algorithmic software functions to sort the usage-value of each block of flash memory so that the system will select the least-used memory block for the next cycle of memory usage. The described system provides direct and immediate access of flash memory to the microprocessor without any intermediate modules or vias which would delay that access. Further, a minimal amount of overhead header information is only required for each flash memory block thus allowing greater areas of memory usage for instructional code data.

Abstract: In a data processing system having a data processor coupled to a SCSI channel disposed for transmitting and receiving data between the data processor and a peripheral storage subsystem, a bridge controller for expanding the maximum allowable number of disk drives connectable to the SCSI channel. The bridge controller comprises a microprocessor having input/output terminals coupled to a CPU bus; a memory having input/output terminals coupled to a DMA bus; a buffer coupled between the CPU bus and the DMA bus; a first transceiver coupled between the DMA bus and the SCSI channel; a second transceiver coupled between the DMA bus and the disk drives; and, a circuit for controlling the direction of data flow through the buffer. The circuit has input/output terminals coupled to the CPU bus and a control output coupled to a direction control input terminal of the buffer.

Abstract: A sub-assembly for transferring heat between a heat generating unit and heat receiving unit which are separated by a gap, comprises: a compliant body having microscopic voids therethrough; a liquid metal alloy that is absorbed in the microscopic voids in the compliant body; a seal ring which surrounds the compliant body; and, a retaining member which is attached to the compliant body and the seal ring, and which holds the compliant body spaced apart from the seal ring. This sub-assembly is placed in the gap between the two units and compressed to the point where liquid metal alloy is squeezed out of the compliant body. Squeezing liquid metal alloy from the compliant body lowers the thermal resistance between the heat generating unit and the heat receiving unit by increasing the area through which heat is transferred and by increasing the thermal conductivity through the compliant body.

Abstract: Within an integrated circuit chip, digital logic gates are intercoupled by signal lines called nets. If one net (called the "victim net") has several segments that respectively lie next to several other nets (called "aggressor nets"), then a certain amount of crosstalk voltage will be coupled into the victim net by each of the aggressor nets; and that can cause a malfunction. But with the present invention, a process is provided whereby an integrated circuit chip is physically laid out and built such that the total crosstalk voltage which is coupled into the victim net by all of the aggressor nets is kept within an acceptable level. This process includes a repetitive cycle where during each cycle, a previously tried layout is modified, and the crosstalk which is coupled into the victim net in the modified layout is estimated by means of an equation.

Abstract: A processor cache memory system utilizes separate cache controllers for independently managing even and odd input address requests with the even and odd address requests being mapped into the respective controllers. Each cache controller includes tag RAM for storing address tags, including a field for storing the least significant address bit, so that the stored tags distinguish between the odd and even addresses. Upon failure of a cache controller, both the even and odd addresses are directed to the operational controller and the stored least significant bit address tag distinguishes between the odd and even input addresses to appropriately generate HIT/MISS signals. The controllers include block address counter logic for generating respective even and odd invalidation addresses for simultaneously performing invalidation cycles thereon when both controllers are operational.

Abstract: A method and implementation is supplied for the synchronous loading and integrity checking of registers located in two different integrated circuit chips. Thus in a computer system having cache memory where the cache memory is sliced into two portions, one of which holds even addresses and the other of which holds odd addresses, there is provided two individual chips each of which has a program word address register which is loaded at the exact same period of time and which is additionally incremented in both cases at the exact same period of time. Further means are provided for checking the integrity of the program word address registers in the first slice and the second slice of the cache in order to insure that they are coherent, or if not coherent, then a disable signal will prevent usage of the address data involved.

Abstract: A single chip data path gate array interface links a central processing unit, operating at a first clock rate and single word protocol, to dual system busses operating at a second clock rate and multiple-word protocol. The data path interface holds command, data and message registers, controlled by external logic, in an input channel pathway and an output channel pathway. The interface chip is basically limited to registers and multiplexers making it flexible for use in different architectures such as both Store-Through and Non-Store-Through cache protocols. In addition, such a simplified chip is simple to fabricate and to maintain free of defects.

Abstract: The present invention is useful in a data processing system having a data processor coupled to a SCSI channel disposed for transmitting and receiving data between the data processor and a peripheral storage subsystem having a multiplicity of disk drives. A method for assuring fair access to all disk drives connected to the SCSI channel by assigning a weighted value to I/O commands when they are issued to the SCSI device. The weighted value is determined on the basis of the length of the data to be transferred by the device. The greater the length of the data to be transferred, the larger the weighted value assigned thereto.