Abstract: A through substrate via (TSV) die includes a substrate including a topside semiconductor surface having active circuitry. The die includes a plurality of TSVs that each include an inner metal core that extend from the topside semiconductor surface to protruding TSV tips that extend out from the bottomside surface. A metal cap is on the protruding TSV tips that includes at least one metal layer that has a metal that is not in the inner metal core. A plurality of protruding warpage control features are on the bottomside surface lateral to the protruding TSV tips, wherein the plurality of protruding warpage control features do not have the protruding TSV tips thereunder. The plurality of protruding warpage control features can include the same metal layer(s) used for the metal cap.

Abstract: A method of testing electronic assemblies including singulated TSV die attached to a ML package substrate, on a substrate carrier. The substrate carrier includes through-holes for allowing probe contact to the BGA substrate pads on a bottomside of the package substrate that are coupled to the frontside of the TSVs. Contactable TSV tips on the bottomside of the TSV die are contacted with a topside coupler that includes a pattern of coupling terminals that matches a layout of at least a portion of the TSV tips or pads coupled to the TSV tips. The topside coupler electrically connects pairs of coupling terminals to provide a plurality of TSV loop back paths. The BGA substrate pads are contacted with a plurality of probes tips that extend through the through-holes to couple to the frontside of the TSVs. Electrical testing is performed across the electronic assembly to obtain at least one test parameter.

Abstract: The present invention relates to methods and arrangements for using a thin foil to form electrical interconnects in an integrated circuit package. One such arrangement involves a foil carrier structure, which includes a foil adhered to a carrier having cavities. Some methods of the present invention involve attaching dice to the foil and encapsulating the foil carrier structure in a molding material. In one embodiment, the molding material presses against the foil, which causes portions of the foil to distend into the cavities of the carrier. As a result, recessed and raised areas are formed in the foil. Afterwards, the carrier is removed and portions of the raised areas in the foil are removed through one of a variety of techniques, such as grinding. This process helps define and electrical isolate contact pads in the foil. The resulting molded foil structure may then be singulated into multiple semiconductor packages.

Abstract: In at least some embodiments, a wireless communication system includes a transmitter that transmits a signal over a communication channel. The system also includes a receiver that receives the signal as an output of the communication channel. The receiver establishes a boundary for a transformed lattice and eliminates candidates outside the established boundary.

Abstract: An integrated circuit package that comprises a lead frame 105, an integrated circuit located on the lead frame and a shunt resistor coupled to the integrated circuit. The shunt resistor has a lower temperature coefficient of resistance than the lead frame, and the lead frame has a lower resistivity than the shunt resistor. The shunt resistor has a low-resistance coupling to external leads of the lead frame, or, the shunt resistor has its own integrated external leads.

Abstract: A method of through substrate via (TSV) die assembly includes positioning a plurality of TSV die with their topside facing down onto a curable bonding adhesive layer on a carrier. The plurality of TSV die include contactable TSVs that include or are coupled to bondable bottomside features protruding from its bottomside. The curable bonding adhesive layer is cured after the positioning. A plurality of second IC die each having a plurality of second bonding features are bonded onto the plurality of TSV die to form a plurality of stacked die assemblies on the carrier. Debonding after the bonding separates the carrier from the plurality of stacked die assemblies. The plurality of stacked die assemblies are then singulated to form a plurality of singulated stacked die assemblies.

Abstract: A hermetic MEMS device (100) comprising a carrier (110) having a surface (111) including a device (101) and an attachment stripe (122), the stripe spaced from the device and surrounding the device; a metallic foil (102) having a central bulge portion (103) and a peripheral rim portion (104) meeting the stripe, the bulge cross section parallel to the carrier monotonically decreasing from the rim (104) towards the bulge apex (105); and the foil positioned over the carrier surface so that the bulge arches over the device and the rim forms a seal with the stripe.

Abstract: The symbolization of a semiconductor device (100) is incorporated in a thin sheet (130) attached to the top of the device, facing outwardly with its bare surface. The material of the sheet (about 1 to 10 ?m thick) includes regions of a first optical reflectivity and a first color, and regions (133) of a second optical reflectivity and a second color, which differ from, and contrast with, the first reflectivity and color. Preferred choices for the sheet material include the compound o-cresol novolac epoxy and the compound bisphenol-A, more preferably with the chemical imidazole added to the film material. A preferred embodiment of the invention is a packaged device with a semiconductor chip a (101) connected to a substrate (102); the connection is achieved by bonding wires (111) forming an arch with a top 111a. The chip, the wire arches, and the substrate are embedded in an encapsulation material (120), which borders on the attached top sheet so that the arch tops touch the border (131).

Abstract: An electronic package 100 comprising a semiconductor device 105, a heat spreader layer 110, and a thermal interface material layer 115 located between the semiconductor device and the heat spreader layer. The thermal interface material layer includes a resin layer 120 having heat conductive particles 125 suspended therein. A portion of the particles are exposed on at least one non-planar surface 135 of the resin layer such that the portion of exposed particles 130 occupies a majority of a total area of a horizontal plane 140 of the non-planar surface.

Abstract: A wirebond-less packaged semiconductor device includes a plurality of I/O contacts, at least one semiconductor die, the semiconductor die having a bottom major surface and a top major surface, the top major surface having at least two electrically isolated electrodes, and a conductive clip system disposed over the top major surface, the clip system comprising at least two electrically isolated sections coupling the electrodes to respective I/O contacts.

Abstract: In accordance with various embodiments, multiple beacons are transmitted in each communication superframe within a wireless network. In accordance with one embodiment, for example, a method is disclosed that comprises transmitting a first beacon in a superframe and transmitting a second beacon in the superframe. The first beacon comprises wireless medium access information that specifies nodes that are to communicate across a wireless medium in that superframe. The second beacon also comprises wireless medium access information. The first and second beacons further specify a list of nodes that are to transmit the first beacons in subsequent superframes upon failure to receive the first beacon for a corresponding predetermined number of superframes.

Abstract: A system for synchronizing a wireless receiver is provided. The system includes a first antenna and a second antenna to receive independent wireless signals containing different combination of data packets. The system includes one or more analyzer components operable to determine correlation metrics based on at least a portion of the first received signal and a portion of the second received signal. The system further includes a synchronization component operable to use the correlation metrics to determine a preferred correlation metric for synchronization by the wireless receiver of the first and second received signals to decode the data packet. A method for synchronizing a receiver of two wireless signals is also provided.

Abstract: Systems and methods for identifying a transmission channel response and a feedback channel response from a plurality of composite system responses are disclosed. A plurality of shifted feedback signals are created by shifting a feedback signal frequency by a plurality of first offset values and/or by shifting a transmission signal frequency by a plurality of second offset values. The feedback signals are compared to an input signal to identify the transmission channel response and/or a feedback channel response. A control signal is generated for a pre-distortion circuit to modify the input signal by an inverse of the transmission channel response. The composite system response is measured at a plurality of operating frequencies and at the plurality of offset values. The measurements are stored in a matrix and singular value decomposition is applied to the matrix of measurements to calculate the transmission channel response and feedback channel response.

Abstract: A method in accordance with an embodiment of the invention includes producing a first signal match indication based on at least one match indication indicative of a match between at least one signal received in at least one band and a reference signal. The method also includes producing a first signal multipath combined signal based upon the first signal match indication, and detecting a first peak in the first multipath combined signal.

Abstract: An IC includes a substrate having a semiconductor top surface and a bottom surface, wherein the semiconductor top surface includes one or more active circuit components and a plurality of through silicon vias (TSVs) extending through the substrate. The plurality of TSVs include an outer dielectric liner. The dielectric liner includes at least one halogen or a Group 15 element metal gettering agent in an average concentration from 1 to 10 atomic %. A metal diffusion barrier layer is on the dielectric liner and a metal filler is on the metal barrier layer. The metal gettering agent getters metal filler that escapes the metal barrier layer.

Abstract: A packaged semiconductor device includes a semiconductor die including a substrate having a topside including active circuitry and a bottomside with at least one backside metal layer directly attached. A package including a molding material having a die pad and a plurality of leads is encapsulated within the molding material, wherein the leads include an exposed portion that includes a bonding portion. The topside of the semiconductor die is attached to the die pad, and the package includes a gap that exposes the backside metal layer along a bottom surface of the package. Bond wires couple pads on the topside of the semiconductor die to the leads. The bonding portions, the molding material along the bottom surface of the package, and the backside metal layer are all substantially planar to one another.

Abstract: A semiconductor device with a sheet-like insulating substrate (101) integral with two or more patterned layers of conductive lines and vias, a chip attached to an assembly site, and contact pads (103) in pad locations has an encapsulated region on the top surface of the substrate, extending to the edge of the substrate, enclosing the chip, and having contact apertures (703) at the pad locations for external communication with the pad metal surfaces. The apertures may have not-smooth sidewall surfaces and may be filled with solder material (704) to contact the pads. Metal-filled surface grooves (710) in the encapsulated region, with smooth groove bottom and sidewalls, are selected to serve as customized routing interconnections, or redistribution lines, between selected apertures and thus to facilitate the coupling with another semiconductor device to form a package-on-package assembly.

Abstract: An integrated circuit (IC) device includes a substrate having a top surface including active circuitry including a plurality of I/O nodes, and a plurality of die pads coupled to the plurality of I/O nodes. A first dielectric layer including first dielectric vias is over the plurality of die pads. A redirect layer (RDL) including a plurality of RDL capture pads is coupled to the plurality of die pads over the first dielectric vias. A second dielectric layer including second dielectric vias is over the plurality of RDL capture pads. At least one of the second dielectric vias is a crack arrest via that has a via shape that includes an apex that faces away from a neutral stress point of the IC die and is oriented along a line from the neutral stress point to the crack arrest via to face in a range of ±30 degrees from the line. Under bump metallization (UBM) pads are coupled to the plurality of RDL capture pads over the second dielectric vias, and metal bonding connectors are on the UBM pads.

Abstract: Embodiments of the invention provide a system and method to improve the performance of a GNSS receiver using antenna switching. The system has a plurality of antennas and at least one radio frequency RF chain. There are fewer RF chain(s) than antennas. A receiver processes a plurality of signals sent by a plurality of transmitters. The system also includes antenna switches and switch controller. The method includes processing signals from a plurality of satellite vehicles SVs using an antenna selected from a plurality of antennas.

Abstract: A layered message updating method and system for the decoding of LDPC codes with high sub-matrix degree has a scalable foldable and flexible decoder architecture to support LDPC codes with arbitrary high sub-matrix degree with very small hardware overhead and high throughput. Embodiments of the invention support LDPC codes with sub-matrix degree W=>1.