Abstract: A microelectronic integrated circuit includes a semiconductor substrate, and a plurality of CMOS microelectronic devices formed on the substrate. Each device includes a triangular ANY element of a first conductivity type (PMOS or NMOS), and a triangular ALL element of a second conductivity type (NMOS or PMOS), the ANY and ALL elements each having a plurality of inputs and an output that are electrically interconnected respectively. The ANY element is basically an OR element, and the ALL element is basically an AND element. However, the power supply connections and the selection of conductivity type (NMOS or PMOS) for the ANY and ALL elements can be varied to provide the device as having a desired NAND, AND, NOR or OR configuration, in which the ANY element acts as a pull-up and the ALL element acts as a pull-down, or vice-versa.

Abstract: A method of making, including a method of floorplanning, an integrated circuit includes the separation of electrical logic function cells of the integrated circuit into sets or macros of data path cells, each of which evidence a high level of similarity or repetitiveness in the integrated circuit, and into sets of random logic cells, which each are connected to data path cells but which do not meet topological and connectivity criteria for the data path cells. The data path cells are iteratively sorted according to connectivity requirements and are initially placed on a provisional floor plan of the integrated circuit in a cell-space matrix of rows and columns, the rows being of substantially uniform width to accommodate functional modules of the data path cells, and the rows being of variably height to cooperatively define the spaces of the cell-space matrix.