Abstract: A processor natively executes lookup instructions. The lookup instruction is decoded to determine which general-purpose register (GPR) contains a pointer to a lookup key in a buffer. A variable-length key is read from the buffer and hashed to generate an index into a first-level cache and a hashed tag. An address of a bucket of entries for the index is generated and tags from these entries are read and compared to the hashed tag. When an entry matches the hashed tag, a second-level entry is read. A stored key from the second-level entry is compared to the input key to determine a match. The addresses of the matching second-level and first-level entries are written to GPR's specified by operands decoded from the lookup instruction. When the key or entry data is long, the second-level entry also contains a pointer to a key extension or data extension in a third-level cache.

Abstract: An optical-disk play-back system has a lens that receives a light beam reflected from a data surface of an optical disk. The lens focuses the light on four quadrant photodiodes. The position of the lens relative to the photodiodes is adjusted by a standard tracking control loop. In addition, the sledge position is controlled by a sledge-center-error signal. Since the sledge position changes only infrequently, the center error is a low-frequency signal. A non-linear center-error-generating circuit uses two op-amp stages. Signals from an inner pair of photodiodes are summed and applied to one input of the first-stage op amp, while signals from an outer pair of photodiodes are summed and applied to the other input of the first-stage op amp. The first-stage op amp output an overall error signal that includes high-frequency errors. A high-pass filter removes low-frequency components output from the first-stage op amp. The high-pass filter drives an inverting input of the second-stage op amp.

Abstract: A parity generating circuit that can replace the parity bit DRAM on a 9-bit SIMM. The parity generating circuit includes a parity generating tree which outputs the resulting even parity from the 8 data bits on a read. A 9th data input from another parity generator on the system mother board is compared to the generator tree output when DRAM is written to. If a mismatch occurs, the type of parity generated by the generator tree is opposite to the type of parity that the mother board generates, and the parity tree output must be inverted on subsequent reads. A latch is provided to store the compare result, which also indicates the type of parity required, even or odd, on the particular system the SIMM is installed on. The latch is loaded when the DRAM is written to. The state of the latch is used to output the correct type of parity on a read from DRAM by inverting the output of the parity generating circuit if needed.