Abstract: Manufacturing yield is increased and cost lowered when a second, substantially identical CPU core is placed on a microprocessor die when the die contains a large cache. The large cache is shared among the two CPU cores. When one CPU core is defective, the large cache memory may be used by the other CPU core. Thus having two complete CPU cores on the die greatly increases the probability that the large cache can be used, and the manufacturing yield is therefore increased. When both CPU cores are functional, the die may be sold as a dual-processor. However, when no dual-processor chips are to be sold, the die are still manufactured as dual-processor die but packaged only as uni-processor chips. With the higher total yield of the dual-CPU die, the dual-CPU die may be packaged solely as uni-processor chips at lower cost than using uni-processor die. An on-chip ROM for generating test vectors, a floating point unit, and a bus-interface unit are also shared along with the large cache.

Abstract: A dual-instruction set central processing unit (CPU) is capable of executing instructions from a reduced instruction set computer (RISC) instruction set and from a complex instruction set computer (CISC) instruction set. Data and address information may be transferred from a CISC program to a RISC program running on the CPU by using shared registers. The architecturally-defined registers in the CISC instruction set are merged or folded into some of the architecturally-defined registers in the RISC architecture so that these merged registers are shared by the two instructions sets. In particular, the flags or condition code registers defined by each architecture are merged together so that CISC instructions and RISC instructions will implicitly update the same merged flags register when performing computational instructions.